MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1041

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.3.1.1.2
The CFG_DATA register is shown in
Table 16-5
The CFG_DATA register is a 4-byte window into the little-endian PCI configuration header data structure;
therefore, byte addressing within the CFG_DATA register uses little-endian convention. Note that
CFG_DATA may contain 1, 2, 3, or 4 bytes depending on the size of the register being accessed.
See
Accessing the PCI Configuration Space,”
16.3.1.1.3
An external PCI interrupt acknowledge transaction is generated by reading the INT_ACK register. For
PCI, INT_ACK is at offset 0x008. INT_ACK is shown in
Table 16-6
16.3.1.2
The outbound address translation and mapping unit controls the mapping of transactions from the internal
platform address space to the external PCI address space. The outbound ATMU consists of four translation
windows plus a default translation for transactions that do not hit in one of the four windows.
Freescale Semiconductor
Offset 0x004
Offset 0x008
Reset
Reset
Section 16.4.2.11.2, “Host Accessing the PCI Configuration Space,”
W
W
R
R
0
0
0–31
Bits
describes the bit settings for the CFG_DATA register
describes the bit settings for the INT_ACK register.
PCI ATMU Outbound Registers
PCI Configuration Data Register (CFG_DATA)
PCI Interrupt Acknowledge Register (INT_ACK)
Name
Data
0–31 Data A read to this register generates a PCI interrupt acknowledge cycle.
Bits Name
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
A read or write to this register starts a PCI configuration cycle if the PCI CFG_ADDR
enable bit is set. If the enable bit is not set, a PCI I/O transaction is generated.
Table 16-5. PCI CFG_DATA Field Descriptions
Table 16-6. PCI INT_ACK Field Descriptions
Figure 16-4. PCI CFG_DATA Register
Figure 16-5. PCI INT_ACK Register
Figure
for usage of CFG_DATA.
16-3.
All zeros
All zeros
Description
Data
Data
Description
Figure
16-5.
and
Section 16.4.2.11.3, “Agent
Access: Read/Write
Access: Read Only
PCI Bus Interface
16-15
31
31