MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 221

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 6
L2 Look-Aside Cache/SRAM
This chapter describes the organization of the on-chip L2/SRAM, cache coherency rules, cache line
replacement algorithm, cache control instructions, and various cache operations. It also describes the
interaction between the L2/SRAM and the e500 core complex.
6.1
The integrated 512-Kbyte L2 cache is organized as 2048 eight-way sets of 32-byte cache lines based on
36-bit physical addresses, as shown in
The SRAM can be configured with memory-mapped registers as externally accessible memory-mapped
SRAM in addition to or instead of cache. The L2 cache can operate in the following modes, described in
Section 6.2, “L2 Cache and SRAM
Freescale Semiconductor
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Full cache mode (512-Kbyte cache).
Full memory-mapped SRAM mode (512-Kbyte SRAM mapped as a single 512-Kbyte block or
two 256-Kbyte blocks)
Partial SRAM and partial cache mode, in which one eighth, one quarter, or one half the total
on-chip memory can be allocated to 1 or 2 SRAM regions.
L2 Cache Overview
Independently programmable
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
WR IN
as L2 cache or SRAM
Eight 64-Kbyte banks
L2 Cache/SRAM
512-Kbyte
(8-way)
DOUT
Figure 6-1. L2 Cache/SRAM Configuration
Organization”:
RD IN
Figure
128
6-1.
128
64
32-Kbyte L1
Data Cache
e500 Core Complex
Core Complex Bus
Coherency Module
RD1
e500 Core
RD2
Instruction Cache
32-Kbyte L1
WR
6-1