MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1502

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Global Utilities
23-10
Bits
2–4
6–7
8–9
5
SRDS2_IO_SEL SerDes2 I/O port selection
Name
ECP1
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
000:
Reserved
001:
SATA1
SATA2
eTSEC1 and eTSEC3 Ethernet interface uses parallel interface according to POR config inputs
cfg_tsec1_prtcl and cfg_tsec3_prtcl.
010:
Reserved
011:
SATA1
SATA2 disabled.
eTSEC1 and eTSEC3 Ethernet interface uses parallel interface according to POR config inputs
cfg_tsec1_prtcl and cfg_tsec3_prtcl.
SerDes2 Lane B disabled.
100:
SATA1 and SATA2 disabled.
eTSEC1 SGMII (1.25 Gbps)
eTSEC3 SGMII (1.25 Gbps)
POR config inputs cfg_tsec1_prtcl and cfg_tsec3_prtcl should be left in their default settings.
101:
Reserved
110:
SATA1 and SATA2 disabled.
eTSEC1 SGMII (1.25 Gbps)
its default setting)
eTSEC3 parallel mode Ethernet interface (according to cfg_tsec3_prtcl).
SerDes2 Lane B disabled
111:
SATA1 and SATA2 disabled.
eTSEC1 and eTSEC3 Ethernet interface uses parallel interface according to POR config inputs
cfg_tsec1_prtcl and cfg_tsec3_prtcl.
SerDes2 disabled
Reserved
eTSEC1 controller protocol (See
00 The eTSEC1 controller operates using the 8-bit FIFO protocol.
01 The eTSEC1 controller operates using the MII protocol (or RMII if configured in reduced mode).
10 The eTSEC1 controller operates using the GMII protocol (or RGMII if configured in reduced
11 The eTSEC1 controller operates using the TBI protocol (or RTBI if configured in reduced mode).
Reserved
Table 23-7. PORDEVSR Field Descriptions (continued)
mode).
SerDes2 Lane A.
SerDes2 Lane B.
SerDes2 Lane A.
SerDes2 Lane A.
SerDes2 Lane A (POR config input cfg_tsec1_prtcl should be left in
SerDes2 Lane B.
Section 4.4.3.16, “eTSEC1
Description
Protocol.”)
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