MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1610

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Debug Features and Watchpoint Facility
Figure 25-21
Table 25-28
Figure 25-22
25-28
Reset
Reset
W
10–13
14–18
19–31
32–63
R
W
R
Bits
0–4
5–9
14–18
19–31
32–63
Bits
PCITT
DDRTT DDRSID
0
0
Table 25-27. CMD Trace Buffer Entry Field Descriptions (TBCR1[IFSEL] = 000) (continued)
DDRADDR
CMDADDR
DDRSID
DDRBC
DDRTT
4
describes the fields of DDR SDRAM trace buffer entries when TBCR1[IFSEL] = 001.
4
Name
CMDBC
shows the trace buffer entry format for the DDR SDRAM interface, TBCR1[IFSEL] = 001.
shows the PCI trace buffer entry format when TBCR1[IFSEL] = 010 or 101.
Name
Table 25-28. DDR Trace Buffer Entry Field Descriptions (TBCR1[IFSEL] = 001)
—
—
PCISID PCIBC
—
5
5
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
9
9
Transaction type. Specifies the transaction type as shown in
zeros maps to write.
Source ID. Specifies the source of the transaction as shown in
010101 indicates that DMA is the transaction source, and so on.
Reserved
Byte count
Reserved
Address bits 0–31
Byte count. Range: 32 to 1 where a value of 0 indicates 32 bytes.
00000 = 32 bytes
00001 = 1 byte
00010 = 2 bytes
11110 = 30 bytes
11111 = 31 bytes
Reserved
· · ·
Address bits 0–31
10
10
—
11
13
12
DDRBC
14
Figure 25-21. DDR Trace Buffer Entry
Figure 25-22. PCI Trace Buffer Entry
18
—
19
—
31
31
All zeros
All zeros
32
32
Function
Function
Table
DDRADDR
Table
PCIADDR
25-12. For example, a value of all
25-26. For example, a value of
Freescale Semiconductor
63
63