MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1029

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

example, consider the case where a core writes data to a PCI device and then updates a flag in the local
DDR memory indicating the write to PCI has completed. An external PCI master may misread the flag
ahead of the actual write transaction's completion on the PCI bus.
There are two blocks of memory in the design:
There are many blocks of control logic in the block. On the PCI side there are machines for PCI controller
initiated address and data tenures for inbound and outbound data, respectively. On the OCeaN side there
are machines for fabric arbitration, outbound data, and inbound data.
As an initiator, the integrated processor supports read and write operations to the PCI memory space, the
PCI I/O space, and the 256-byte PCI configuration space. As an initiator, the integrated processor also
supports generating PCI special-cycle and interrupt-acknowledge transactions. As a target, the integrated
processor supports read and write operations to local memory, and, when configured in agent mode, read
and write operations to the internal PCI configuration registers.
The integrated processor can function as either a PCI host bridge (host mode) or a peripheral device on the
PCI bus (agent mode). See
In agent mode, all of the PCI configuration registers in the integrated processor can be programmed from
the PCI bus. See
information.
The PCI interface provides bus arbitration for the integrated processor and up to five other PCI bus
masters. The arbitration algorithm is a programmable two-level, round-robin priority selector. The on-chip
PCI arbiter can operate in both host and agent modes or it can be disabled to allow for an external PCI
arbiter.
The integrated processor also provides an address translation mechanism to map inbound PCI to OCeaN
accesses and outbound OCeaN to PCI accesses.
16.1.1.1
Upon detecting an OCeaN-to-PCI transaction, the integrated processor requests the use of the PCI bus. For
OCeaN-to-PCI bus write operations, the integrated processor requests mastership of the PCI bus when the
source completes the write operation to the OCeaN. For OCeaN-to-PCI read operations, the integrated
processor requests mastership of the PCI bus when it decodes that the access is for PCI address space.
Once granted, the integrated processor drives the address (PCI_AD[31:0]) and the bus command
(PCI_C/BE[3:0]) signals.
The master part of the interface can initiate master-abort cycles, recognizes target-abort, target-retry, and
target-disconnect cycles, and supports various device selection timings. The master interface does not run
fast back-to-back or exclusive accesses.
Freescale Semiconductor
•
•
The inbound buffers
The outbound read buffers combined with the outbound write buffers
Outbound Transactions
Section 16.4.2.11.3, “Agent Accessing the PCI Configuration Space,”
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Section 16.1.3.1.1, “Host Mode,”
for more information.
for more
PCI Bus Interface
16-3