MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 496

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
10.7.1.8
The AESU interrupt mask register, controls the setting of bits in the AESU interrupt status register, as
described in
set, then the corresponding interrupt status register bit is always zero.
As shown in
register.
10-66
Offset 0x3_4038
Reset
W
0–48
R
Bits
49
50
51
52
53
54
55
56
0
Table 10-28
Section 10.7.1.7, “AESU Interrupt Status
Figure
AESU Interrupt Mask Register
Name
ERE
KSE
DSE
ICE
ME
CE
—
—
IE
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
10-27, the interrupt mask register has the same field designations as the interrupt status
describes the AESU interrupt mask register fields.
Table 10-28. AESU Interrupt Mask Register Field Descriptions
Reserved
Integrity Check Error. The supplied ICV did not match the one computed by the AESU.
0 Integrity check error enabled.
1 Integrity check error disabled
Note: ICE should not be enabled if using EU status writeback (see bits IWSE and AWSE
Reserved
Internal Error. An internal processing error was detected while the AESU was processing.
0 Internal error enabled
1 Internal error disabled
Early Read Error. An AESU context register was read while the AESU was processing.
0 Early read error enabled
1 Early read error disabled
Context Error. An AESU key register or the key size register, data size register, mode
register, or IV register was modified while the AESU was processing.
0 Context error enabled
1 Context error disabled
Key Size Error. An inappropriate value (non 16, 24 or 32 bytes) was written to the AESU
key size register
0 Key size error enabled
1 Key size error disabled
Data Size Error. Indicates that the number of bits to process is out of range.
0 Data size error enabled
1 Data size error disabled
Mode Error. Indicates that invalid data was written to a register or a reserved mode bit was
set.
0 Mode error enabled
1 Mode error disabled
—
Figure 10-27. AESU Interrupt Mask Register
in
Section 10.4.4.1, “Channel Configuration Register
48
ICE — IE ERE CE KSE DSE ME AE OFE IFE — IFO OFU —
49
50 51
Register”. If an AESU interrupt mask register bit is
1000
Description
52
53
54
55
(CCR)”).
56
57
Freescale Semiconductor
58
Access: Read/Write
59 60
61
62
63