MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 521

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Offset 0x3_8018
10.7.2.4
This register, as shown in
self-clearing bits. It should be noted that the AFEU executes an internal reset sequence for hardware reset,
SW_RESET, or module initialization, which performs proper initialization of the S-box. To determine
when this is complete, observe the RESET_DONE bit in the AFEU status register.
Reset
Table 10-38
10.7.2.5
This status register, shown in
The AFEU status register is read only. Writing to this location results in address error being reflected in
the AFEU interrupt status register.
Freescale Semiconductor
Offset 0x3_8010
Reset
W
W
R
R
0–60
0
Bits
0
61
62
63
describes AFEU reset control register fields.
AFEU Reset Control Register
AFEU Status Register
Name
SR
MI
—
RI
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 10-38. AFEU Reset Control Register Field Descriptions
Figure
Reserved
Reset Interrupt. Writing this bit active high causes AFEU interrupts signaling done and
error to be reset. It further resets the state of the AFEU interrupt status register.
0 Do not reset
1 Reset interrupt logic
Module initialization resets everything reset by SR, with the exception of the AFEU interrupt
mask register.
0 Do not reset
1 Reset most of AFEU
Software reset is functionally equivalent to hardware reset (the RESET# pin), but only for
AFEU. All registers and internal state are returned to their defined reset state. On negation
of SW_RESET, the AFEU enters a routine to perform proper initialization of the S-box.
0 Do not reset
1 Full AFEU reset
Figure 10-34. AFEU Context/Data Size Register
Figure
Figure 10-35. AFEU Reset Control Register
10-35, allows 3 levels reset that effect the AFEU only, as defined by 3
10-36, reflect the state of AFEU internal signals.
—
—
All zeros
All zeros
Description
51 52
Security Engine (SEC) 3.0
Access: Read/Write
Access: Read/Write
Data Size
60
61
RI MI SR
62
10-91
63
63