MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 470

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
Table 10-12
options; and
10-40
CCR bit 60
AWSE
1
2
1
0
0
0
0
Bits
WARNING: When using reset bits R, CON and NPR: the configuration register must be polled to confirm completion
of the multi-cycle reset sequence. The length of time required for this reset sequence depends on several factors
and should be considered indeterminate. Completion is indicated by the self-clearing of the asserted reset bit.
Failure to ensure completion of reset prior to writing to the channel may result in a channel hang condition.
WARNING: The done interrupt, done writeback, and status writeback do not occur if an EU produces an error
interrupt to the channel. In particular, if the ICV check error interrupt is enabled in the EU (see the ICE bit in the EU’s
interrupt mask register), and the ICV check finds a mismatch, then the channel produces an error interrupt but no
channel done interrupt or writebacks.
60
61
62
63
CCR bit 59
CDWE
shows the CCR and descriptor header bit settings for different descriptor header writeback
Table 10-13
1
1
1
x
x
AWSE
Name
CDIE
NT
—
CCR bit 56
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
IWSE
Table 10-11. Channel Configuration Register Fields (continued)
x
x
x
x
1
shows the bit settings for different done interrupt generation options.
Always writeback status enable.
0 No special action.
1 At the completion of processing each descriptor, the channel writes back to the
descriptor header the DONE, ICCR0, and ICCR1 fields (see
IWSE has no effect.
Notification type. This bit controls when the channel generates channel done notification.
Channel done notification can take the form of an interrupt and/or modified header
writeback, depending on the state of the CDIE and CDWE control bits.
0 Global notification: The channel generates channel done notification (if enabled) at the
end of each descriptor.
1 Selected notification: The channel generates channel done notification (if enabled) at
the end of every descriptor with the DN bit set in the descriptor header.
0 Channel done interrupt disabled
1 Channel done interrupt enabled. Upon successful completion of descriptor processing,
if the NT bit is cleared (for global notification), or if the DN (done notification) bit is set in the
header word of the descriptor, then a channel done interrupt is asserted to notify the host.
Refer to
interrupt operation.
Reserved, should be set to zero.
Channel done interrupt enable.
CCR bit 61
NT
x
1
1
0
x
Section 10.4.4, “Channel
Table 10-12. Writeback Options
Header bit 63
DN
0
1
x
x
x
2
write back header fields DONE, ICCR0, ICCR1
no writeback performed
write back header field DONE
write back header field DONE
if the descriptor header indicates ICV checking in AESU, CRCU,
KEU, or MDEU, then write back header fields DONE, ICCR0, and
ICCR1.
Writeback Action for a Descriptor completing without error
Registers,” for a complete description of channel done
Description
Table
10-5). In this case,
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2