MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 321

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.4.1.26
The DDRDSR_2 register, shown in
impedance for the DDR drivers for clocks.
Table 8-32
8.4.1.27
DDRCDR_1, shown in
P/N impedance, ODT termination value for IOs, driver software override enable for MDIC, driver
software override enable for address/command, driver software override enable for data, the DDR
address/command driver P/N impedance, and the DDR data driver P/N impedance.
The fields in DDRCDR_1, other than DDRCDR_1[ODT], are used to enable driver calibration with the
MDIC[0:1] pins. This can be used to calibrate the DDR drivers to 18 ohms. However, this should only be
used for full-strength driver applications.
Hardware DDR driver calibration is enabled by setting DDRCDR_1[DHC_EN].
Software can be used to calibrate the drivers instead of the automatic hardware calibration. If software
calibration is used, the following steps should be taken:
Freescale Semiconductor
Offset 0xB24
Reset
1. Set DDRCDR_1[DSO_MDIC_EN] and ensure that DDRCDR_1[DHC_EN] is cleared
2. Set the highest impedance (value 0000) for DDRCDR_1[DSO_MDICPZ]
3. Set DDRCDR_1[DSO_MDIC_PZ_OE] to enable the output enable for MDIC[0]
4. After at least 4 cycles, read DDRDSR_1[0]. If the value is 0, then use the next lowest impedance,
W
R
and read DDRDSR_1[0] again. Once a value of 1 is detected, then leave
DDRCDR_1[DSO_MDICPZ] at the calibrated value
0
8–31
Bits
0–3
4–7
describes the DDRDSR_2 fields.
CLKPZ
DDR Debug Status Register 2 (DDRDSR_2)
DDR Control Driver Register 1 (DDRCDR_1)
All driver calibration, whether by software or hardware, should be done
before the DDR controller is enabled (before
DDR_SDRAM_CFG[MEM_EN] is set).
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
3
CLKNZ
CLKPZ
Name
—
4
Figure
Figure 8-27. DDR Debug Status Register 2 (DDRDSR_2)
CLKNZ
8-28, sets the driver hardware compensation enable, the DDR MDIC driver
Table 8-32. DDRDSR_2 Field Descriptions
Current setting of PFET driver clock impedance
Current setting of NFET driver clock impedance
Reserved
7
Figure
8
8-27, contains the current settings of the P and N FET
NOTE
All zeros
Description
DDR Memory Controller
Access: Read only
31
8-47