MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1379

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.5.3.2
DWords 1–8 constitute eight slots of transaction control and status. Each transaction description includes:
The host controller uses the information in each transaction description, plus the endpoint information
contained in the first three DWords of the buffer page pointer list, to execute a transaction on the USB.
Freescale Semiconductor
31–5
Bits
4–3
2–1
0
•
•
•
Status results field
Transaction length (bytes to send for OUT transactions and bytes received for IN transactions).
Buffer offset. The PG and Transaction n Offset fields are used with the buffer pointer list to
construct the starting buffer address for the transaction.
Link Pointer Correspond to memory address signals [31:5], respectively. This field points to another isochronous
Name
Typ
—
T
iTD Transaction Status and Control List
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
transaction descriptor (iTD/siTD) or queue head (QH).
Reserved, should be cleared. These bits are reserved and their value has no effect on operation.
Software should initialize this field to zero.
Indicates to the host controller whether the item referenced is an iTD, siTD or a QH. This allows the host
controller to perform the proper type of processing on the item after it is fetched. Value encodings are:
00 iTD (isochronous transfer descriptor)
01 QH (queue head)
10 siTD (split transaction isochronous transfer descriptor)
11 FSTN (frame span traversal node)
Terminate
1 Link Pointer field is not valid.
0 Link Pointer field is valid.
Table 21-38. Next Schedule Element Pointer
Description
Universal Serial Bus Interfaces
21-45