MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 486

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
10-56
32–39
40–47
48–55
56–63
Bits
30
31
CHN3_BUS_PR_CNT Channel 3 Bus Priority Count. In weighted priority arbitration, this field gives the number
CHN4_BUS_PR_CNT Channel 4 Bus Priority Counter. In weighted priority arbitration, this field gives the number
CHN3_EU_PR_CNT
CHN4_EU_PR_CNT
By default, All SEC memory transactions are snooped by the coherency
module of the MPC85xx. This is part of the wiring of the SEC interface and
requires no user intervention. Bit 30 in the MCR is used to inhibit cache
snooping of SEC transactions in non-MPC85xx situations.
Name
SWR
GIH
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 10-21. Master Control Register Fields (continued)
Global Inhibit. Setting this bit indicates that SoC master bus transfers are defined as not
snoopable and results in lowering the snoop attribute of bus requests generated by the
external gasket (see note following table).
0 SoC master bus transfers are defined as snoopable (default)
1 SoC master bus transfers are defined as not snoopable
Software Reset. Setting this bit causes a global software reset. Upon completion of the
reset, this bit is automatically cleared.
0 Do not reset
1 Global reset
Channel 3 EU Priority Count. In weighted priority arbitration, this field gives the number of
times that Channel 3 is denied access for a requested EU before its priority is elevated
(see
Note: If both CHN3_EU_PR_CTR and CHN4_EU_PR_CTR are zero, the controller
Channel 4 EU Priority Count. In weighted priority arbitration, this field gives the number of
times that Channel 4 is denied access for a requested EU before its priority is elevated
(see
Note: If both CHN3_EU_PR_CTR and CHN4_EU_PR_CTR are zero, the controller
of times that Channel 3 is denied access to the polychannel before its priority is elevated
(see
Note: If both CHN3_BUS_PR_CTR and CHN4_BUS_PR_CTR are zero, the controller
of times that Channel 4is denied access to the polychannel before its priority is elevated
(see
If both CHN3_BUS_PR_CTR and CHN4_BUS_PR_CTR are zero, the controller assigns
the polychannel on a pure round-robin basis. If either of these counters is zero and the
other is non-zero, then the zero is interpreted as 256.
Section 10.5.2.2, “Weighted Priority
Section 10.5.2.2, “Weighted Priority
Section 10.5.2.2, “Weighted Priority
Section 10.5.2.2, “Weighted Priority
assigns EU’s on a pure round-robin basis. If either of these counters is zero and the
other is non-zero, then the zero is interpreted as 256.
assigns EU’s on a pure round-robin basis. If either of these counters is zero and the
other is non-zero, then the zero is interpreted as 256.
assigns the polychannel on a pure round-robin basis. If either of these counters is
zero and the other is non-zero, then the zero is interpreted as 256.
NOTE
Description
Arbitration”).
Arbitration”).
Arbitration”).
Arbitration”).
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