MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 63

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure
Number
13-11
13-12
13-13
13-14
13-15
13-16
13-17
13-18
13-19
13-20
13-21
13-22
13-23
13-24
13-25
13-26
13-27
13-28
13-29
13-30
13-31
13-32
13-33
13-34
13-35
13-36
13-37
13-38
13-39
13-40
13-41
13-42
13-43
13-44
13-45
Freescale Semiconductor
Basic eLBC Bus Cycle with LALE, TA, and LCSn ........................................................... 13-46
Special Operation Initiation Register (LSOR) .................................................................... 13-25
UPM Refresh Timer (LURT) .............................................................................................. 13-25
Transfer Error Status Register (LTESR) ............................................................................. 13-26
Transfer Error Check Disable Register (LTEDR) ............................................................... 13-28
Transfer Error Interrupt Enable Register (LTEIR).............................................................. 13-29
Transfer Error Attributes Register (LTEATR...................................................................... 13-30
Transfer Error Address Register (LTEAR) ......................................................................... 13-31
Transfer Error ECC Register (LTECCR) ............................................................................ 13-32
Local Bus Configuration Register....................................................................................... 13-32
Clock Ratio Register (LCRR) ............................................................................................. 13-34
Flash Mode Register ........................................................................................................... 13-35
Flash Instruction Register ................................................................................................... 13-37
Flash Command Register .................................................................................................... 13-38
Flash Block Address Register ............................................................................................. 13-39
Flash Page Address Register, Small Page Device (ORx[PGS] = 0) ................................... 13-39
Flash Page Address Register, Large Page Device (ORx[PGS] = 1) ................................... 13-39
Flash Byte Count Register .................................................................................................. 13-41
Flash ECC Blockn Register (FECC0–FECC3)................................................................... 13-41
Basic Operation of Memory Controllers in the eLBC ........................................................ 13-43
Example of 8-Bit GPCM Writing 32 Bytes to Address 0x5420 (LCRR[PBYP] = 0) ........ 13-45
eLBC Bus Cycles in PLL Mode (GPCM and UPM only) .................................................. 13-48
eLBC Bus Cycles in PLL-bypassed Mode (GPCM and UPM only) .................................. 13-48
Enhanced Local Bus to GPCM Device Interface................................................................ 13-49
GPCM Basic Read Timing (XACS = 0, ACS = 1x, TRLX = 0) ........................................ 13-49
GPCM General Read Timing Parameters ........................................................................... 13-50
GPCM General Write Timing Parameters .......................................................................... 13-51
GPCM Basic Write Timing
GPCM Relaxed Timing Back-to-Back Reads
GPCM Relaxed Timing Back-to-Back Writes
GPCM Relaxed Timing Write
GPCM Relaxed Timing Write
GPCM Read Followed by Read (TRLX = 0, EHTR = 0, Fastest Timing) ......................... 13-57
GPCM Read Followed by Write
External Termination of GPCM Access.............................................................................. 13-58
(XACS = 0, ACS = 00, CSNT = 1, SCY = 1, TRLX = 0) ............................................. 13-53
(XACS = 0, ACS = 1x, SCY = 1, CSNT = 0, TRLX = 1, EHTR = 0) .......................... 13-54
(XACS = 0, ACS = 1x, SCY = 0, CSNT = 0, TRLX = 1) ............................................. 13-55
(XACS = 0, ACS = 10, SCY = 0, CSNT = 1, TRLX = 1) ............................................. 13-55
(XACS = 0, ACS = 00, SCY = 1, CSNT = 1, TRLX = 1) ............................................. 13-56
(TRLX = 0, EHTR = 1, One-Cycle Extended Hold Time on Reads) ............................ 13-57
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
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