MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1421

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The scheduling cases are:
Freescale Semiconductor
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Periodic Schedule
Case 1: The normal scheduling case is where the entire split transaction is completely bounded by
a frame (H-Frame in this case).
Case 2a through Case 2c: The USB 2.0 hub pipeline rules states clearly, when and how many
complete-splits must be scheduled to account for earliest to latest execution on the full/low-speed
link. The complete-splits may span the H-Frame boundary when the start-split is in micro-frame 4
or later. When this occurs, the H-Frame to B-Frame alignment requires that the queue head be
reachable from consecutive periodic frame list locations. System software cannot build an efficient
schedule that satisfies this requirement unless it uses FSTNs.
layout of the periodic schedule.
HS/FS/LS Bus
End of Frame
End of Frame
End of Frame
Normal Case
Micro-Frame
Micro-Frame
Case 2a:
Case 2b:
Case 2c:
Case 1:
B-Frame N–1
Figure 21-52. Split Transaction, Interrupt Scheduling Boundary Conditions
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
7
6
0
7
S
1
0
2
1
C0
3
2
H-Frame N
C1
4
3
B-Frame N
C2
S
5
4
S
6
5
C0
Figure 21-53
S
7
6
C0
C1
Universal Serial Bus Interfaces
0
7
C0
C1
C2
illustrates the general
1
0
C1
C2
B-Frame N+1
21-87