MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1279

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.4
Table 20-2
name, and a cross-reference to the complete description of each register. Note that the full register address
is comprised of CCSRBAR together with the eSDHC block base address and offset listed in
Undefined 4-byte address spaces within offset 0x000–0xFFF are reserved.
Freescale Semiconductor
1
The addresses following 0x044, except 0x050, 0x0FC and 0x40C, are reserved and read as all 0s. Writes to these registers
are ignored.
0x044
Offset
0x00C
0x01C
0x02C
0x03C
0x0FC
0x40C
0x000
0x004
0x008
0x010
0x014
0x018
0x020
0x024
0x028
0x030
0x034
0x038
0x040
0x050
1
Memory Map/Register Definition
shows the memory mapped registers of the eSDHC module and their offsets. It lists the offset,
All eSDHC registers must be accessed as aligned 4-byte quantities.
Accesses to the eSDHC registers that are less than 4-bytes are not supported.
DMA system address (DSADDR)
Block attributes (BLKATTR)
Command argument (CMDARG)
Command transfer type (XFERTYP)
Command response0 (CMDRSP0)
Command response1 (CMDRSP1)
Command response2 (CMDRSP2)
Command response3 (CMDRSP3)
Data buffer access port (DATPORT)
Present state (PRSSTAT)
Protocol control (PROCTL)
System control (SYSCTL)
Interrupt status (IRQSTAT)
Interrupt status enable (IRQSTATEN)
Interrupt signal enable (IRQSIGEN)
Auto CMD12 status (AUTOC12ERR)
Host controller capabilities (HOSTCAPBLT)
Watermark level (WML)
Force event (FEVT)
Host controller version (HOSTVER)
DMA control register (DCR)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
eSDHC Registers—Block Base Address 0x2_E000
Register
Table 20-2. eSDHC Memory Map
NOTE
Access
Mixed
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
w1c
W
R
R
R
R
R
R
R
R
0x117F_013F
0x01E3_0000
0x0000_0008
0x0000_0008
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x nn 8 n _00 n 0
0x0000_0000
0x0000_8000
0x0000_0000
0x0000_0000
0x0000_0000
0x0010_0010
0x0000_0000
0x0000_0001
0x0000_0000
Enhanced Secure Digital Host Controller
Reset
Section/Page
20.4.10/20-22
20.4.11/20-26
20.4.12/20-29
20.4.13/20-31
20.4.14/20-33
20.4.15/20-34
20.4.16/20-34
20.4.17/20-36
20.4.18/20-37
20.4.5/20-11
20.4.5/20-11
20.4.5/20-11
20.4.5/20-11
20.4.6/20-12
20.4.7/20-13
20.4.8/20-17
20.4.9/20-19
20.4.1/20-6
20.4.2/20-6
20.4.3/20-7
20.4.4/20-8
Table
20-2.
20-5