MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 732

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Local Bus Controller
or not. This feature allows the synchronous negation of LUPWAIT to affect a data transfer, even if UTA,
WAEN, and LAST are set simultaneously.
13.4.4.6
Slow memory devices that take a long time to turn off their data bus drivers on read accesses should choose
some non-zero combination of ORn[TRLX] and ORn[EHTR]. The next accesses after a read access to the
slow memory device is delayed by the number of clock cycles specified in the ORn register in addition to
any existing bus turnaround cycle.
13.5
13.5.1
This section provides guidelines for interfacing to peripherals.
13.5.1.1
In order to reduce pins on the local bus, address and data signals are multiplexed. To build the address, an
external latch is used to demultiplex and reconstruct the original address. Since the LALE signal provides
the correct timing to control a standard logic latch, no external intelligence is needed. To pass data, the
LAD signals can be directly connected to the data signals of the memory/peripheral.
Transactions on the local bus begin with an address phase. The eLBC drives the transaction address on the
LAD signals and asserts the LALE signal to latch the address. This assertion causes address bits A[0:31]
to appear on LAD[0:31]. The eLBC can then continue on into the data phase.
The eLBC supports port sizes of 8, 16, and 32 bits. When there is an access larger than the port size, the
eLBC breaks up the access into smaller transactions using the non-multiplexed address signals LAn. For
32-bit devices, LA[30:31] are irrelevant since these address bits are implicit in the byte lanes which carry
data. Similarly, for 16-bit devices, LA[30] is used and LA[31] is irrelevant; however, for 8-bit devices,
LA[30:31] are necessary.
In addition, the eLBC supports burst transfers in the UPM machine. To minimize the amount of address
phases needed on the local bus and to optimize the throughput, LAn are driven separatelyand should be
used whenever a device requires the five least-significant addresses. The five least-significant address bits
13-90
Initialization/Application Information
Interfacing to Peripherals in Different Address Modes
Extended Hold Time on Read Accesses
Multiplexed Address/Data Bus for 32-Bit Addressing
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Freescale Semiconductor