MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 427

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In general, these signals should be considered mutually exclusive. If a PCI Express INTx signal is being
used, the PIC must be configured so that external interrupts are level sensitive (EIVPRn[S] = 1). If an IRQn
signal is being used as edge-triggered (EIVPRn[S] = 0), the system must not allow inbound PCI Express
INTx transactions.
Note that it is possible to share IRQn and INTx if the external interrupt is level sensitive; however, if an
interrupt occurs, the interrupt service routine must poll both the external sources connected to the IRQn
input and the PCI Express INTx sources to determine from which path the external interrupt came. In any
case, IRQn should be pulled to the negated state as determined by the associated polarity setting in
EIVPRn[P].
9.4.6
There are appropriate clock prescalers and synchronizers to provide a time base for the internal PIC timers.
These 8 timers are organized as 2 groups of 4 timers each. The timers can be individually programmed to
generate a processor core interrupt when they count down to zero and can be used to generate regular
periodic interrupts. Each timer has the following four configuration and control registers:
The timer frequency should be written to the TFRRxn, described in
Reporting Register
Timer interrupts are all edge-triggered interrupts. If a timer period expires while a previous interrupt from
the same source is pending or in service, the subsequent interrupt is lost.
The timer control register (TCR) provides users with the ability to create timers larger than the 31-bit
global timers. The timer frequency can also be changed by setting the appropriate TCR fields, as described
in
9.4.7
This section describes the behavior of the PIC at reset and the PIC’s ability to initiate processor resets.
Freescale Semiconductor
Section 9.3.2.6, “Timer Control Registers
•
•
•
•
Global timer current count register (GTCCRxn)
Global timer base count register (GTBCRxn)
Global timer vector-priority register (GTVPRxn)
Global timer destination register (GTDRxn)
Global Timers
Resets
(TFRRA–TFRRB).”
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 9-50. PCI Express INTx/IRQ n Sharing (continued)
PCI Express Number
PCI Express 3
(TCRA–TCRB).”
INTC
INTD
INTx
INTA
INTB
IRQ10
IRQ11
IRQ n
IRQ8
IRQ9
Section 9.3.2.1, “Timer Frequency
Programmable Interrupt Controller (PIC)
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