MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 79

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure
Number
23-25
23-26
23-27
23-28
23-29
23-30
23-31
23-32
23-33
23-34
23-35
23-36
24-1
24-2
24-3
24-4
24-5
24-6
24-7
24-8
24-9
24-10
24-11
25-1
25-2
25-3
25-4
25-5
25-6
25-7
25-8
25-9
25-10
25-11
25-12
25-13
25-14
25-15
25-16
25-17
25-18
Freescale Semiconductor
Clock Out Control Register (CLKOCR)............................................................................. 23-33
ECM Control Register (ECMCR)....................................................................................... 23-33
General Control Register (GCR)......................................................................................... 23-34
SerDes1 Control Register 0 (SRDS1CR0).......................................................................... 23-35
SerDes1 Control Register 2 (SRD1SCR2).......................................................................... 23-37
SerDes2 Control Register 0 (SRDS2CR0).......................................................................... 23-39
SerDes2 Control Register 1 (SRDS2CR1).......................................................................... 23-41
SerDes2 Control Register 2 (SRDSCR2)............................................................................ 23-42
SerDes2 Control Register 3 (SRDS2CR3).......................................................................... 23-44
e500 Core Power Management State Diagram ................................................................... 23-48
MPC8536E Power Management Handshaking Signals...................................................... 23-53
Power Supply Switch for MPC8536E ................................................................................ 23-60
Performance Monitor Block Diagram................................................................................... 24-2
Performance Monitor Global Control Register (PMGC0).................................................... 24-5
Performance Monitor Local Control Register A0 (PMLCA0) ............................................. 24-6
Performance Monitor Local Control A Registers (PMLCA1–PMLCA9)............................ 24-7
Performance Monitor Local Control Register B0 (PMLCB0).............................................. 24-8
Performance Monitor Local Control Register B (PMLCB1–PMLCB9) .............................. 24-9
Performance Monitor Counter Register 0 (PMC0)............................................................. 24-10
Performance Monitor Counter Register (PMC1–PMC9) ................................................... 24-11
Duration Threshold Event Sequence Timing Diagram ....................................................... 24-13
Burst Size, Distance, Granularity, and Burstiness Counting............................................... 24-14
Burstiness Counting Timing Diagram ................................................................................ 24-16
Debug and Watchpoint Monitor Block Diagram .................................................................. 25-2
Watchpoint Monitor Control Register 0 (WMCR0) ........................................................... 25-10
Watchpoint Monitor Control Register 1 (WMCR1) ........................................................... 25-12
Watchpoint Monitor Address Register (WMAR) ............................................................... 25-12
Watchpoint Monitor Address Mask Register (WMAMR).................................................. 25-13
Watchpoint Monitor Transaction Mask Register (WMTMR)............................................. 25-13
Watchpoint Monitor Status Register (WMSR) ................................................................... 25-15
Trace Buffer Control Register 0 (TBCR0).......................................................................... 25-15
Trace Buffer Control Register 1 (TBCR1).......................................................................... 25-17
Trace Buffer Address Register (TBAR).............................................................................. 25-18
Trace Buffer Address Mask Register (TBAMR) ................................................................ 25-18
Trace Buffer Transaction Mask Register (TBTMR) ........................................................... 25-19
Trace Buffer Status Register (TBSR).................................................................................. 25-19
Trace Buffer Access Control Register (TBACR) ............................................................... 25-20
Trace Buffer Read High Register (TBADHR).................................................................... 25-21
Trace Buffer Access Data Register (TBADR) .................................................................... 25-22
Programmed Context ID Register (PCIDR) ....................................................................... 25-22
Current Context ID Register (CCIDR) ............................................................................... 25-23
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figures
Title
Number
Page
lxxix