MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 124

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Overview
The MPC8536E supports a flexible 36-bit physical address map. Conceptually, the address map consists
of local space and external address space. The local address map is supported by ten local access windows
that define mapping within the local 36-bit (64-Gbyte) address space.
The MPC8536E can be made part of a larger system address space through the mapping of translation
windows. This functionality is included in the address translation and mapping units (ATMUs). Both
inbound and outbound translation windows are provided. The ATMUs allows the MPC8536E to be part of
larger address maps such as the PCI Express 64-bit address environment.
1.3.3
The SEC 3.0 off-loads computationally intensive security functions, such as key generation and exchange,
authentication, and bulk encryption from the processor cores of the MPC8536E. It is optimized to process
all cryptographic algorithms associated with IPsec, IKE, SSL/TLS, iSCSI, SRTP, 802.11i, 3G, A5/3 for
GSM and EDGE, and GEA3 for GPRS. The SEC 3.0 derives from integrated security cores in other
members of the PowerQUICC family, including the SEC 2.1 Rev2 in the MPC8548E and the SEC 1.0 in
the MPC8272E.
Components of the SEC are as follows:
1.3.4
The MPC8536E offers two high-speed SerDes interface blocks. These blocks are connected to the SGMII,
PCI Express, and SATA interfaces as described in this section.
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XOR engine for parity checking in RAID storage applications. Also, the exclusive OR (XOR)
operation to generate parity data in RAID applications can be accelerated. XOR operations use
SEC descriptors and offload both parity generation and data movement from the e500 core.
Four crypto-channels, each supporting multi-command descriptor chains.
Eight cryptographic execution units:
— Advanced Encryption Standard unit (AESU)
— ARC four execution unit (AFEU)
— Cyclic redundancy check accelerator (CRCA)
— Data Encryption Standard execution unit (DEU)
— Kasumi execution unit (KEU)
— Message digest execution unit (MDEU)
— Public key execution unit (PKEU)
— Random number generator (RNGB)
Integrated Security Engine (SEC)
High-Speed Interface Blocks (SerDes)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Freescale Semiconductor