MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1525

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.4.1.25 Clock Out Control Register (CLKOCR)
Shown in
the clock out (CLK_OUT) signal.
Table 23-28
23.4.1.26 ECM Control Register (ECMCR)
Shown in
USB3 and ESDHC address bus for all transaction initiated by these blocks.
Freescale Semiconductor
Offset 0xE20
Offset 0xE00
Reset
Reset
Reset
26–31 CLK_SEL Clock out select
1–25
Bits
W
W
W
R
R
R
0
ENB
0
16
Figure
Figure
0
SATA1_UPRADR
describes the bit settings of CLKOCR.
USB1_UPRADR
1
Name
ENB
—
23-25, the CLKOCR contains control bits that select the clock sources to be placed on
23-26, the ECMCR contains the uppermost bits of the SATA1, SATA2, USB1, USB2,
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Clock out enable
0 CLK_OUT signal is three-stated
1 CLK_OUT signal is driven according to CLKOCR[CLK_SEL]
Reserved
000000 CCB (platform) clock
000001 CCB (platform) clock divided by 2
000010 SYSCLK (echoes SYSCLK input)
000011 SYSCLK divided by 2 (demonstrates
All other values are reserved
Figure 23-25. Clock Out Control Register (CLKOCR)
19
3
platform PLL lock)
Figure 23-26. ECM Control Register (ECMCR)
Table 23-28. CLKOCR Field Descriptions
20
4
SATA2_UPRADR
USB2_UPRADR
—
All zeros
All zeros
23
All zeros
7
Description
24
8
USB3_UPRADR
10x010 PCI bus clock
10x011 PCI bus clock divided by 2
11
—
12
ESDHC_UPRADR
25 26
Access: Read/Write
CLK_SEL
Global Utilities
Read/Write
15
31
23-33
31