MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet

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... MPC8536E PowerQUICC III™ Integrated Processor Reference Manual Supports MPC8536E MPC8535E MPC8536ERM Rev. 1 05/2009 ...

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... All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. All rights reserved. Document Number: MPC8536ERM Rev. 1, 05/2009 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...

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... Power Management Controller.................................................................................... 1-7 1.3.9 PCI Express Controller ................................................................................................ 1-8 1.3.10 Programmable Interrupt Controller (PIC).................................................................... 1-8 1.3.11 Enhanced Secure Digital Host Controller (eSDHC).................................................... 1-8 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Contents About This Book Part I Overview ...

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... Organization of CCSR Memory ................................................................................ 2-11 2.3.4 General Utilities Registers ......................................................................................... 2-12 2.3.5 Interrupt Controller and CCSR .................................................................................. 2-13 2.3.6 Device-Specific Utilities............................................................................................ 2-13 2.4 Complete CCSR Map .................................................................................................... 2-14 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev Contents Title 2 C, DUART, eLBC ........................................................................ 1-9 Chapter 2 Memory Map Page ...

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... Boot ROM Location .............................................................................................. 4-14 4.4.3.7 Host/Agent Configuration ..................................................................................... 4-15 4.4.3.8 SerDes1 I/O Port Selection.................................................................................... 4-16 4.4.3.9 SerDes2 I/O Port Selection.................................................................................... 4-17 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 3 Signal Descriptions Chapter 4 Reset, Clocking, and Initialization ...

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... Boot ROM..................................................................................................... 4-35 4.5.1.2.1 Overview ........................................................................................................... 4-35 4.5.1.2.2 Features.............................................................................................................. 4-36 4.5.1.2.3 EEPROM Data Structure................................................................................... 4-36 4.5.1.2.4 eSPI Controller Configuration........................................................................... 4-40 4.5.1.3 Default e500 Addressing During System Boot ..................................................... 4-41 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev Contents Title Page Number Freescale Semiconductor ...

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... L2 Cache Timing ........................................................................................................... 6-27 6.6 L2 Cache and SRAM Coherency................................................................................... 6-27 6.6.1 L2 Cache Coherency Rules........................................................................................ 6-28 6.6.2 Memory-Mapped SRAM Coherency Rules .............................................................. 6-29 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Part II e500 Core Complex and L2 Cache Chapter 5 e500 Core Integration Details ...

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... ECM Error Enable Register (EEER) ....................................................................... 7-7 7.2.1.7 ECM Error Attributes Capture Register (EEATR) .................................................. 7-7 7.2.1.8 ECM Error Low Address Capture Register (EELADR) ......................................... 7-8 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 viii Contents Title Part III Memory, Security, and I/O Interfaces ...

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... DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL) ............................. 8-34 8.4.1.16 DDR Initialization Address (DDR_INIT_ADDR)................................................ 8-34 8.4.1.17 DDR Initialization Enable Extended Address (DDR_INIT_EXT_ADDR) .......... 8-35 8.4.1.18 DDR SDRAM Timing Configuration 4 (TIMING_CFG_4)................................. 8-36 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 8 DDR Memory Controller Page ...

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... DDR SDRAM Refresh and Power-Saving Modes ................................................ 8-80 8.5.8.2.1 Self-Refresh in Sleep Mode............................................................................... 8-82 8.5.9 DDR Data Beat Ordering........................................................................................... 8-83 8.5.10 Page Mode and Logical Bank Retention ................................................................... 8-83 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev Contents Title Page Number Freescale Semiconductor ...

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... Spurious Vector Register (SVR)............................................................................ 9-23 9.3.2 Global Timer Registers .............................................................................................. 9-23 9.3.2.1 Timer Frequency Reporting Register (TFRRA–TFRRB) ..................................... 9-24 9.3.2.2 Global Timer Current Count Registers (GTCCRA0–GTCCRA3, GTCCRB0–GTCCRB3)..................................................................................... 9-24 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 9 Page Number xi ...

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... Who Am I Registers 0–1 (WHOAMI0–WHOAMI1) ........................................... 9-50 9.3.8.4 Processor Core Interrupt Acknowledge Registers 0–1 (IACK0–IACK1)............. 9-50 9.3.8.5 Processor Core End of Interrupt Registers (EOI0–EOI1) ..................................... 9-51 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xii Contents Title Page Number Freescale Semiconductor ...

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... Cyclical Redundancy Check Unit (CRCU) ......................................................... 10-10 10.1.4.8 Random Number Generator Unit (RNGU).......................................................... 10-11 10.2 Configuration of Internal Memory Space .................................................................... 10-11 10.3 Descriptors ................................................................................................................... 10-19 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 10 Security Engine (SEC) 3.0 Page Number ...

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... System Bus Master Write—Detailed Description ........................................... 10-48 10.5.2 Arbitration Algorithms ............................................................................................ 10-48 10.5.2.1 Round-Robin Arbitration..................................................................................... 10-48 10.5.2.2 Weighted Priority Arbitration .............................................................................. 10-48 10.5.3 Controller Interrupts ................................................................................................ 10-49 10.5.3.1 Controller Interrupt Conditions and Interrupt Generation................................... 10-49 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xiv Contents Title Page Number Freescale Semiconductor ...

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... AFEU Status Register.......................................................................................... 10-91 10.7.2.6 AFEU Interrupt Status Register........................................................................... 10-92 10.7.2.7 AFEU Interrupt Mask Register............................................................................ 10-94 10.7.2.8 AFEU End of Message Register.......................................................................... 10-96 10.7.2.9 AFEU Context ..................................................................................................... 10-96 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xv ...

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... KEU Interrupt Status Register (KEUISR) ......................................................... 10-123 10.7.5.7 KEU Interrupt Mask Register (KEUIMR) ........................................................ 10-125 10.7.5.8 KEU Data Out Register (f9 MAC) (KEUDOR)................................................ 10-127 10.7.5.9 KEU End of Message Register (KEUEMR) ..................................................... 10-127 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xvi Contents Title Page Number Freescale Semiconductor ...

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... PKEU Parameter Memory N ......................................................................... 10-155 10.7.8 Random Number Generator Unit (RNGU)............................................................ 10-155 10.7.8.1 RNGU Mode Register ....................................................................................... 10-156 10.7.8.2 RNGU Data Size Register ................................................................................. 10-156 10.7.8.3 RNGU Reset Control Register........................................................................... 10-156 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xvii ...

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... Arbitration Procedure .............................................................................................. 11-15 11.4.2.1 Arbitration Control .............................................................................................. 11-15 11.4.3 Handshaking ............................................................................................................ 11-16 11.4.4 Clock Control........................................................................................................... 11-16 11.4.4.1 Clock Synchronization......................................................................................... 11-16 11.4.4.2 Input Synchronization and Digital Filter ............................................................. 11-16 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xviii Contents Title Chapter Interfaces Page Number Freescale Semiconductor ...

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... Modem Control Registers (UMCRn) .................................................................. 12-14 12.3.1.10 Line Status Registers (ULSRn) ........................................................................... 12-15 12.3.1.11 Modem Status Registers (UMSRn) ..................................................................... 12-16 12.3.1.12 Scratch Registers (USCRn) ................................................................................. 12-17 12.3.1.13 DMA Status Registers (UDSRn) ......................................................................... 12-17 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 12 DUART Page Number xix ...

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... UPM Mode Registers (MxMR) ........................................................................... 13-21 13.3.1.5 Memory Refresh Timer Prescaler Register (MRTPR) ........................................ 13-23 13.3.1.6 UPM/FCM Data Register (MDR) ....................................................................... 13-23 13.3.1.7 Special Operation Initiation Register (LSOR)..................................................... 13-24 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev Contents Title Chapter 13 Enhanced Local Bus Controller Page ...

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... FCM Buffer RAM ............................................................................................... 13-61 13.4.3.1.1 Buffer Layout and Page Mapping for Small-Page NAND Flash Devices ...... 13-61 13.4.3.1.2 Buffer Layout and Page Mapping for Large-Page NAND Flash Devices ...... 13-62 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page ...

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... Synchronous Sampling of LUPWAIT for Early Transfer Acknowledge ............ 13-89 13.4.4.6 Extended Hold Time on Read Accesses .............................................................. 13-90 13.5 Initialization/Application Information ......................................................................... 13-90 13.5.1 Interfacing to Peripherals in Different Address Modes ........................................... 13-90 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xxii Contents Title Page Number Freescale Semiconductor ...

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... Ethernet Control Register (ECNTRL) ............................................................. 14-35 14.5.3.1.7 Pause Time Value Register (PTV) ................................................................... 14-37 14.5.3.1.8 DMA Control Register (DMACTRL) ............................................................. 14-38 14.5.3.1.9 TBI Physical Address Register (TBIPA) ......................................................... 14-40 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 14 Page Number xxiii ...

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... MAC Configuration 1 Register (MACCFG1)................................................. 14-74 14.5.3.5.2 MAC Configuration 2 Register (MACCFG2)................................................. 14-76 14.5.3.5.3 Inter-Packet Gap/Inter-Frame Gap Register (IPGIFG) ................................... 14-78 14.5.3.5.4 Half-Duplex Register (HAFDUP) ................................................................... 14-79 14.5.3.5.5 Maximum Frame Length Register (MAXFRM) ............................................. 14-80 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xxiv Contents Title Page Number Freescale Semiconductor ...

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... Receive Fragments Counter (RFRG) .............................................................. 14-98 14.5.3.6.23 Receive Jabber Counter (RJBR)...................................................................... 14-99 14.5.3.6.24 Receive Dropped Packet Counter (RDRP)...................................................... 14-99 14.5.3.6.25 Transmit Byte Counter (TBYT) .................................................................... 14-100 14.5.3.6.26 Transmit Packet Counter (TPKT).................................................................. 14-100 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xxv ...

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... Timer Event Mask Register (TMR_TEMASK) ............................................ 14-125 14.5.3.11.4 Timer PTP Packet Event Register (TMR_PEVENT) .................................... 14-126 14.5.3.11.5 Timer Event Mask Register (TMR_PEMASK) ............................................ 14-127 14.5.3.11.6 Timer Status Register (TMR_STAT) ............................................................. 14-128 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xxvi Contents Title Page Number Freescale Semiconductor ...

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... SGMII Interface................................................................................................. 14-156 14.6.2 Connecting to FIFO Interfaces .............................................................................. 14-156 14.6.2.1 Flow Control...................................................................................................... 14-157 14.6.2.2 CRC Appending and Checking ......................................................................... 14-157 14.6.2.3 8-Bit GMII-Style Packet FIFO Mode................................................................ 14-158 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xxvii ...

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... Filer Example—802.1p Priority Filing.......................................................... 14-187 14.6.5.2.7 Filer Example—IP Diff-Serv Code Points Filing.......................................... 14-188 14.6.5.2.8 Filer Example—TCP and UDP Port Filing .................................................. 14-188 14.6.5.3 Transmission Scheduling................................................................................... 14-189 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xxviii Contents Title Page Number Freescale Semiconductor ...

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... FIFO Mode ............................................................................................... 14-232 14.7.1.8 SGMII Interface Support ................................................................................... 14-234 15.1 Introduction.................................................................................................................... 15-1 15.1.1 Block Diagram........................................................................................................... 15-1 15.1.2 Overview.................................................................................................................... 15-2 15.1.3 Features...................................................................................................................... 15-2 15.1.4 Modes of Operation ................................................................................................... 15-2 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 15 DMA Controller Page Number xxix ...

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... Channel Abort...................................................................................................... 15-31 15.4.1.6 Bandwidth Control............................................................................................... 15-31 15.4.1.7 Channel State ....................................................................................................... 15-31 15.4.1.8 Illustration of Stride Size and Stride Distance..................................................... 15-32 15.4.2 DMA Transfer Interfaces ......................................................................................... 15-32 15.4.3 DMA Errors ............................................................................................................. 15-32 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xxx Contents Title Page Number Freescale Semiconductor ...

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... PCI Outbound Window Attributes Registers (POWARn)............................... 16-17 16.3.1.3 PCI ATMU Inbound Registers............................................................................. 16-19 16.3.1.3.1 PCI Inbound Translation Address Registers (PITARn)................................... 16-20 16.3.1.3.2 PCI Inbound Window Base Address Registers (PIWBARn) .......................... 16-20 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title C ......................................................................................................... 15-39 Chapter 16 PCI Bus Interface ...

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... PCI Bus Arbitration ................................................................................................. 16-42 16.4.1.1 PCI Bus Arbiter Operation .................................................................................. 16-43 16.4.1.2 PCI Bus Parking .................................................................................................. 16-44 16.4.1.3 Broken Master Lock-Out ..................................................................................... 16-44 16.4.1.4 Power-Saving Modes and the PCI Arbiter .......................................................... 16-45 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xxxii Contents Title Page Number Freescale Semiconductor ...

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... Agent Mode ......................................................................................................... 16-68 16.5.1.3 Agent Configuration Lock Mode......................................................................... 16-68 16.5.2 Byte Ordering .......................................................................................................... 16-69 16.5.2.1 Byte Order for Configuration Transactions ......................................................... 16-70 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 17 PCI Express Interface Controller Page Number xxxiii ...

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... PCI Express Inbound ATMU Registers ............................................................... 17-25 17.3.5.2.1 EP Inbound ATMU Implementation................................................................ 17-25 17.3.5.2.2 RC Inbound ATMU Implementation ............................................................... 17-25 17.3.5.2.3 PCI Express Inbound Translation Address Registers (PEXITARn)................ 17-26 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xxxiv Contents Title Page Number Freescale Semiconductor ...

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... PCI Express BIST Register—0x0F ................................................................. 17-51 17.3.8.2 Type 0 Configuration Header .............................................................................. 17-51 17.3.8.2.1 PCI Express Base Address Registers—0x10–0x27......................................... 17-51 17.3.8.2.2 PCI Express Subsystem Vendor ID Register (EP-Mode Only)—0x2C .......... 17-54 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xxxv ...

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... PCI Express Link Capabilities Register—0x58 .................................................. 17-74 17.3.9.11 PCI Express Link Control Register—0x5C......................................................... 17-74 17.3.9.12 PCI Express Link Status Register—0x5E ........................................................... 17-75 17.3.9.13 PCI Express Slot Capabilities Register—0x60.................................................... 17-76 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xxxvi Contents Title Page Number Freescale Semiconductor ...

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... Byte Order for Configuration Transactions ................................................... 17-101 17.4.1.3 Lane Reversal .................................................................................................... 17-101 17.4.1.4 Transaction Ordering Rules ............................................................................... 17-102 17.4.1.5 Memory Space Addressing................................................................................ 17-102 17.4.1.6 I/O Space Addressing ........................................................................................ 17-102 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xxxvii ...

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... Memory Map/Register Definition ................................................................................. 18-5 18.3.1 Register Descriptions................................................................................................. 18-6 18.3.1.1 eSPI Mode Register (SPMODE) ........................................................................... 18-6 18.3.1.2 eSPI Event Register (SPIE) ................................................................................... 18-6 18.3.1.3 eSPI Mask Register (SPIM)................................................................................... 18-7 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xxxviii Contents Title Chapter 18 Page Number Freescale Semiconductor ...

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... SATA Interface Status Register (SStatus)............................................................ 19-15 19.3.3.2 SATA Interface Error Register (SError) .............................................................. 19-16 19.3.3.3 SATA Interface Control Register (SControl)....................................................... 19-18 19.3.3.4 SATA Interface Notification Register (SNotification)......................................... 19-19 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 19 SATA Controller Page ...

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... Debug Functionality ............................................................................................ 19-40 19.5.1.11 BIST Support ....................................................................................................... 19-41 19.6 PHY Control Layer Overview ..................................................................................... 19-41 19.7 Initialization/Application Information ......................................................................... 19-41 19.7.1 SATA Controller Initialization Steps ....................................................................... 19-41 Enhanced Secure Digital Host Controller MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev Contents Title Chapter 20 Page Number Freescale Semiconductor ...

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... Data Agent ........................................................................................................... 20-42 20.5.4 Clock & Reset Manager........................................................................................... 20-42 20.5.5 Clock Generator....................................................................................................... 20-43 20.5.6 Card Insertion and Removal Detection.................................................................... 20-43 20.5.7 Power Management and Wake-Up Events .............................................................. 20-43 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xli ...

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... Memory Map/Register Definitions ................................................................................ 21-4 21.3.1 Capability Registers................................................................................................... 21-6 21.3.1.1 Capability Registers Length (CAPLENGTH) ....................................................... 21-7 21.3.1.2 Host Controller Interface Version (HCIVERSION) .............................................. 21-7 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xlii Contents Title Chapter 21 Universal Serial Bus Interfaces Page Number Freescale Semiconductor ...

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... PHY Interface .......................................................................................................... 21-41 21.5 Host Data Structures .................................................................................................... 21-41 21.5.1 Periodic Frame List.................................................................................................. 21-42 21.5.2 Asynchronous List Queue Head Pointer.................................................................. 21-43 21.5.3 Isochronous (High-Speed) Transfer Descriptor (iTD)............................................. 21-44 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xliii ...

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... Empty Asynchronous Schedule Detection .......................................................... 21-78 21.6.9.4 Asynchronous Schedule Traversal: Start Event................................................... 21-79 21.6.9.5 Reclamation Status Bit (USBSTS Register)........................................................ 21-79 21.6.10 Managing Control/Bulk/Interrupt Transfers via Queue Heads................................ 21-79 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xliv Contents Title Page Number Freescale Semiconductor ...

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... Port Change Events ....................................................................................... 21-115 21.6.14.2.2 Frame List Rollover....................................................................................... 21-115 21.6.14.2.3 Interrupt on Async Advance.......................................................................... 21-115 21.6.14.2.4 Host System Error ......................................................................................... 21-116 21.7 Device Data Structures .............................................................................................. 21-116 21.7.1 Endpoint Queue Head............................................................................................ 21-117 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xlv ...

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... Managing Transfers with Transfer Descriptors ..................................................... 21-138 21.8.5.1 Software Link Pointers ...................................................................................... 21-138 21.8.5.2 Building a Transfer Descriptor .......................................................................... 21-138 21.8.5.3 Executing a Transfer Descriptor ........................................................................ 21-139 21.8.5.4 Transfer Completion .......................................................................................... 21-139 21.8.5.5 Flushing/De-Priming an Endpoint ..................................................................... 21-140 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xlvi Contents Title Page Number Freescale Semiconductor ...

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... Memory Map/Register Definition ................................................................................. 22-2 22.3.1 GPIO Direction Register (GPDIR) ............................................................................ 22-2 22.3.2 GPIO Open Drain Register (GPODR)....................................................................... 22-3 22.3.3 GPIO Data Register (GPDAT)................................................................................... 22-3 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 22 General Purpose I/O (GPIO) Page ...

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... Machine Check Summary Register (MCPSUMR).............................................. 23-26 23.4.1.17 Reset Request Status and Control Register (RSTRSCR) .................................... 23-27 23.4.1.18 Exception Reset Control Register (ECTRSTCR)................................................ 23-28 23.4.1.19 Automatic Reset Status Register (AUTORSTSR)............................................... 23-28 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xlviii Contents Title Part IV Global Functions and Debug Chapter 23 ...

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... Requirements for Reaching and Recovering from Deep Sleep State .................. 23-56 23.5.1.14 Requirements for Generating Wake-Up Events................................................... 23-57 23.5.1.14.1 USB ................................................................................................................. 23-57 23.5.1.14.2 GPIO ................................................................................................................ 23-58 23.5.1.14.3 Timer................................................................................................................ 23-58 23.5.1.14.4 eTSEC Wake-on LAN—Magic Packet ........................................................... 23-58 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xlix ...

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... Overview.................................................................................................................... 25-1 25.1.2 Features...................................................................................................................... 25-3 25.1.3 Modes of Operation ................................................................................................... 25-3 25.1.3.1 Local Bus (LBC) Debug Mode.............................................................................. 25-4 25.1.3.2 DDR SDRAM Interface Debug Modes ................................................................. 25-4 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev Contents Title Chapter 24 Device Performance Monitor Chapter 25 Page Number Freescale Semiconductor ...

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... Local Bus Interface Debug ...................................................................................... 25-26 25.4.4 Watchpoint Monitor ................................................................................................. 25-26 25.4.4.1 Watchpoint Monitor Performance Monitor Events ............................................. 25-26 25.4.5 Trace Buffer ............................................................................................................. 25-27 25.4.5.1 Traced Data Formats (as a Function of TBCR1[IFSEL]).................................... 25-27 25.5 Initialization ................................................................................................................. 25-30 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number li ...

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... Device Performance Monitor.................................................................................... A-50 A.3.3 Watchpoint Monitor and Trace Buffer...................................................................... A-51 B.1 Changes From Revision 0 to Revision 1 .........................................................................B-1 C.1 Overview of Differences..................................................................................................C-1 C.2 Signal Differences............................................................................................................C-2 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lii Contents Title Appendix A Appendix B Revision History Appendix C MPC8535E ...

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... SerDes2 (SATA) I/O Port Selection.........................................................................C-5 C.4 Differences in Peripheral Blocks .....................................................................................C-5 C.4.1 PCI Express Interfaces.................................................................................................C-5 C.4.2 USB Controllers...........................................................................................................C-5 C.4.3 SATA Controllers.........................................................................................................C-6 C.4.4 eTSEC Controllers.......................................................................................................C-6 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number liii ...

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... Paragraph Number MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 liv Contents Title Page Number Freescale Semiconductor ...

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... Physical Address Usage for L2 Cache Accesses .................................................................... 6-5 6-4 Physical Address Usage for SRAM Accesses ........................................................................ 6-6 6-5 Data Bus Connection of CCB ................................................................................................. 6-8 6-6 Address Bus Connection of CCB............................................................................................ 6-8 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Figures Page Number ...

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... DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) ................................................ 8-19 8-8 DDR SDRAM Timing Configuration 2 Register (TIMING_CFG_2).................................. 8-21 8-9 DDR SDRAM Control Configuration Register (DDR_SDRAM_CFG) .............................. 8-23 8-10 DDR SDRAM Control Configuration Register 2 (DDR_SDRAM_CFG_2)....................... 8-26 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lvi Figures Title Page Number Freescale Semiconductor ...

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... Example 256-Mbyte DDR SDRAM Configuration With ECC ............................................ 8-63 8-49 DDR SDRAM Burst Read Timing—ACTTORW = 3, MCAS Latency = 2 ........................ 8-74 8-50 DDR SDRAM Single-Beat (Double Word) Write Timing—ACTTOR ............................... 8-75 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page ...

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... Message Enable Register (MER) .......................................................................................... 9-35 9-30 Message Status Register (MSR)............................................................................................ 9-36 9-31 Message Signaled Interrupt Registers (MSIRn) ................................................................... 9-37 9-32 Shared Message Signaled Interrupt Status Register (MSISR).............................................. 9-37 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lviii Figures Title Page Number Freescale Semiconductor ...

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... IP Block Revision Register ................................................................................................. 10-54 10-20 Master Control Register ...................................................................................................... 10-55 10-21 AESU Mode Register.......................................................................................................... 10-58 10-22 AESU Key Size Register .................................................................................................... 10-61 10-23 AESU Data Size Register ................................................................................................... 10-61 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lix ...

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... DEU Status Register ......................................................................................................... 10-112 10-61 DEU Interrupt Status Register .......................................................................................... 10-113 10-62 DEU Interrupt Mask Register ........................................................................................... 10-115 10-63 DEU End of Message Register ......................................................................................... 10-116 10-64 KEU Mode Register.......................................................................................................... 10-118 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev Figures Title Page Number Freescale Semiconductor ...

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... PKEU Interrupt Mask Register ......................................................................................... 10-153 10-102 PKEU End of Message Register ....................................................................................... 10-154 10-103 RNGU Mode Register....................................................................................................... 10-156 10-104 RNGU Data Size Register................................................................................................. 10-156 10-105 RNGU Reset Control Register.......................................................................................... 10-156 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lxi ...

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... UPM Mode Registers (MxMR)........................................................................................... 13-21 13-8 Memory Refresh Timer Prescaler Register (MRTPR)........................................................ 13-23 13-9 UPM Data Register in UPM Mode (MDR) ........................................................................ 13-24 13-10 FCM Data Register in FCM Mode (MDR)......................................................................... 13-24 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lxii Figures Title Page Number Freescale Semiconductor ...

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... GPCM Read Followed by Read (TRLX = 0, EHTR = 0, Fastest Timing) ......................... 13-57 13-44 GPCM Read Followed by Write (TRLX = 0, EHTR = 1, One-Cycle Extended Hold Time on Reads) ............................ 13-57 13-45 External Termination of GPCM Access.............................................................................. 13-58 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number ...

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... Single-Beat Write Access to FPM DRAM ....................................................................... 13-101 13-78 Burst Read Access to FPM DRAM Using LOOP (Two Beats Shown)............................ 13-102 13-79 Refresh Cycle (CBR) to FPM DRAM .............................................................................. 13-103 13-80 Exception Cycle ................................................................................................................ 13-104 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lxiv Figures Title Page Number Freescale Semiconductor ...

Page 65

... RBPTR0–RBPTR7 Register Definition .............................................................................. 14-69 14-36 RBASEH Register Definition ............................................................................................. 14-70 14-37 RBASE Register Definition ................................................................................................ 14-70 14-38 TMR_RXTS_H/L Register Definition................................................................................ 14-71 14-39 MACCFG1 Register Definition .......................................................................................... 14-74 14-40 MACCFG2 Register Definition .......................................................................................... 14-76 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lxv ...

Page 66

... Receive Dropped Packet Counter Register Definition ....................................................... 14-99 14-79 Transmit Byte Counter Register Definition ...................................................................... 14-100 14-80 Transmit Packet Counter Register Definition ................................................................... 14-100 14-81 Transmit Multicast Packet Counter Register Definition ................................................... 14-101 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lxvi Figures Title Page Number Freescale Semiconductor ...

Page 67

... TMR_PRSC Register Definition ...................................................................................... 14-130 14-118 TMROFF_H/L Register Definition .................................................................................. 14-131 14-119 TMR_ALARM1-2_H/L Register Definition .................................................................... 14-131 14-120 TMR_FIPERn Register Definition ................................................................................... 14-133 14-121 TMR_ETTS1-2_H/L Register Definition ......................................................................... 14-133 14-122 Control Register Definition............................................................................................... 14-136 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lxvii ...

Page 68

... Mapping of RxBDs Data Structure ........................................................................ 14-206 15-1 DMA Block Diagram............................................................................................................ 15-1 15-2 DMA Operational Flow Chart .............................................................................................. 15-4 15-3 DMA Signal Summary.......................................................................................................... 15-4 15-4 DMA Mode Registers (MRn) ............................................................................................... 15-9 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lxviii Figures Title Page Number Freescale Semiconductor ...

Page 69

... PCI Inbound Window Attributes Registers......................................................................... 16-21 16-15 PCI Error Detect Register (ERR_DR) ................................................................................ 16-24 16-16 PCI Error Capture Disable Register (ERR_CAP_DR) ....................................................... 16-25 16-17 PCI Error Enable Register (ERR_EN)................................................................................ 16-26 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lxix ...

Page 70

... DAC Single-Beat Read Example........................................................................................ 16-57 16-55 DAC Burst Read Example .................................................................................................. 16-57 16-56 DAC Single-Beat Write Example ....................................................................................... 16-58 16-57 DAC Burst Write Example ................................................................................................. 16-58 16-58 Standard PCI Configuration Header ................................................................................... 16-59 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lxx Figures Title Page Number Freescale Semiconductor ...

Page 71

... Internal Source, Outbound Transaction.......................................................................... 17-37 17-29 PCI Express Error Capture Register 0 (PEX_ERR_CAP_R0) External Source, Inbound Transaction ........................................................................... 17-37 17-30 PCI Express Error Capture Register 1 (PEX_ERR_CAP_R1) Internal Source, Outbound Transaction.......................................................................... 17-38 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lxxi ...

Page 72

... PCI Express I/O Base Register ........................................................................................... 17-60 17-64 PCI Express I/O Limit Register .......................................................................................... 17-60 17-65 PCI Express Secondary Status Register.............................................................................. 17-61 17-66 PCI Express Memory Base Register ................................................................................... 17-62 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lxxii Figures Title Page Number Freescale Semiconductor ...

Page 73

... PCI Express Uncorrectable Error Mask Register ............................................................... 17-84 17-105 PCI Express Uncorrectable Error Severity Register ........................................................... 17-85 17-106 PCI Express Correctable Error Status Register................................................................... 17-86 17-107 PCI Express Correctable Error Mask Register ................................................................... 17-86 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lxxiii ...

Page 74

... SPITF Example—SPMODEx[REVx]=1, SPMODEx[LENx]=15, MSB Sent First .......... 18-11 18-13 eSPI Receive Data Register (SPIRF) .................................................................................. 18-11 18-14 SPIRF Example—SPMODEx[LENx]=3............................................................................ 18-11 18-15 SPIRF Example—SPMODEx[LENx]=10.......................................................................... 18-11 18-16 SPIRF Example—SPMODEx[LENx]=15.......................................................................... 18-11 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lxxiv Figures Title Page Number Freescale Semiconductor ...

Page 75

... System Connection of the eSDHC........................................................................................ 20-1 20-2 eSDHC Block Diagram......................................................................................................... 20-2 20-3 DMA System Address Register (DSADDR) ........................................................................ 20-6 20-4 Block Attributes Register (BLKATTR) ................................................................................ 20-6 20-5 Command Argument Register (CMDARG) ......................................................................... 20-7 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lxxv ...

Page 76

... Transmit FIFO Tuning Controls (TXFILLTUNING) ......................................................... 21-22 21-18 ULPI Register Access (ULPI VIEWPORT) ....................................................................... 21-23 21-19 Configure Flag Register (CONFIGFLAG) ......................................................................... 21-24 21-20 Port Status and Control (PORTSC)..................................................................................... 21-25 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lxxvi Figures Title Page Number Freescale Semiconductor ...

Page 77

... Split Transaction State Machine for Isochronous ............................................................. 21-104 21-59 End Point Queue Head Organization ................................................................................ 21-117 21-60 Endpoint Queue Head Layout........................................................................................... 21-118 21-61 Endpoint Transfer Descriptor (dTD)................................................................................. 21-120 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lxxvii ...

Page 78

... System Version Register (SVR).......................................................................................... 23-30 23-22 Reset Control Register (RSTCR)........................................................................................ 23-30 23-23 LBC Voltage Select Control Register (LBCVSELCR)....................................................... 23-31 23-24 DDR Clock Disable Register (DDRCLKDR) .................................................................... 23-32 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lxxviii Figures Title Page Number Freescale Semiconductor ...

Page 79

... Trace Buffer Read High Register (TBADHR).................................................................... 25-21 25-16 Trace Buffer Access Data Register (TBADR) .................................................................... 25-22 25-17 Programmed Context ID Register (PCIDR) ....................................................................... 25-22 25-18 Current Context ID Register (CCIDR) ............................................................................... 25-23 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lxxix ...

Page 80

... Coherency Module Dispatch (CMD) Trace Buffer Entry .......................................... 25-27 25-21 DDR Trace Buffer Entry ..................................................................................................... 25-28 25-22 PCI Trace Buffer Entry ....................................................................................................... 25-28 25-23 PCI Express Trace Buffer Entry.......................................................................................... 25-29 C-1 MPC8535E Block Diagram ....................................................................................................C-2 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lxxx Figures Title Page Number Freescale Semiconductor ...

Page 81

... SerDes2 I/O Port Selection ................................................................................................... 4-17 4-18 CPU Boot Configuration....................................................................................................... 4-18 4-19 Boot Sequencer Configuration.............................................................................................. 4-18 4-20 DDR DRAM Type ................................................................................................................ 4-19 4-21 Serdes 2 Reference Clock Configuration.............................................................................. 4-19 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Tables Page Number lxxxi ...

Page 82

... L2CAPTECC Field Descriptions .......................................................................................... 6-21 6-16 L2ERRDET Field Descriptions ............................................................................................ 6-21 6-17 L2ERRDIS Field Descriptions.............................................................................................. 6-22 6-18 L2ERRINTEN Field Descriptions ........................................................................................ 6-23 6-19 L2ERRATTR Field Descriptions .......................................................................................... 6-23 6-20 L2ERRADDRL Field Description........................................................................................ 6-24 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lxxxii Tables Title Page Number Freescale Semiconductor ...

Page 83

... DDR_SDRAM_MODE_2 Field Descriptions...................................................................... 8-30 8-17 DDR_SDRAM_MD_CNTL Field Descriptions................................................................... 8-31 8-18 Settings of DDR_SDRAM_MD_CNTL Fields .................................................................... 8-32 8-19 DDR_SDRAM_INTERVAL Field Descriptions .................................................................. 8-33 8-20 DDR_DATA_INIT Field Descriptions ................................................................................. 8-33 8-21 DDR_SDRAM_CLK_CNTL Field Descriptions ................................................................. 8-34 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number lxxxiii ...

Page 84

... Example of Address Multiplexing for 64-Bit Data Bus Interleaving between Two Banks with Partial Array Self Refresh Disabled...................................................... 8-68 8-58 Example of Address Multiplexing for 64-Bit Data Bus Interleaving between Four Banks with Partial Array Self Refresh Disabled ....................................... 8-69 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lxxxiv Tables Title Page ...

Page 85

... CISR0 Field Descriptions ..................................................................................................... 9-31 9-25 CISR1 Field Descriptions ..................................................................................................... 9-32 9-26 CISR2 Field Descriptions ..................................................................................................... 9-32 9-27 PMnMR0 Field Descriptions ................................................................................................ 9-33 9-28 PMnMR1 Field Descriptions ................................................................................................ 9-34 9-29 PMnMR2 Field Descriptions ................................................................................................ 9-34 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number lxxxv ...

Page 86

... Fetch FIFO Enqueue Register Field Descriptions .............................................................. 10-44 10-18 Channel Assignment Value ................................................................................................. 10-50 10-19 Field Names in Interrupt Enable, Interrupt Status, and Interrupt Clear Registers .............. 10-51 10-20 IP Block Revision Register Fields ...................................................................................... 10-55 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lxxxvi Tables Title Page Number Freescale Semiconductor ...

Page 87

... KEU IV_1 Register Fields Description ........................................................................... 10-128 10-59 MDEU Mode Register in Old Configuration.................................................................... 10-133 10-60 MDEU Mode Register in New Configuration .................................................................. 10-134 10-61 Mode Register—HMAC or SSL-MAC Generated by Single Descriptor........................ 10-136 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number lxxxvii ...

Page 88

... Parity Selection Using ULCR[PEN], ULCR[SP], and ULCR[EPS] .................................. 12-14 12-15 UMCR Field Descriptions .................................................................................................. 12-14 12-16 ULSR Field Descriptions .................................................................................................... 12-15 12-17 UMSR Field Descriptions................................................................................................... 12-16 12-18 USCR Field Descriptions.................................................................................................... 12-17 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 lxxxviii Tables Title Page Number Freescale Semiconductor ...

Page 89

... Boot Bank Field Values after Reset for GPCM as Boot Controller.................................... 13-59 13-35 FCM Chip-Select to First Command Timing...................................................................... 13-68 13-36 FCM Command, Address, and Write Data Timing Parameters.......................................... 13-69 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page ...

Page 90

... TBPTRn Field Descriptions ................................................................................................ 14-51 14-25 TBASEH Field Descriptions............................................................................................... 14-51 14-26 TBASE0–TBASE7 Field Descriptions ............................................................................... 14-52 14-27 TMR_TXTSn_ID Register Field Descriptions ................................................................... 14-53 14-28 TMR_TXTSn_H/L Register Field Descriptions................................................................. 14-53 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev Tables Title Page Number Freescale Semiconductor ...

Page 91

... TRMAX Field Descriptions................................................................................................ 14-90 14-65 TRMGV Field Descriptions................................................................................................ 14-91 14-66 RBYT Field Descriptions.................................................................................................... 14-91 14-67 RPKT Field Descriptions .................................................................................................... 14-92 14-68 RFCS Field Descriptions .................................................................................................... 14-92 14-69 RMCA Field Descriptions .................................................................................................. 14-93 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number xci ...

Page 92

... CAM2 Field Descriptions ................................................................................................. 14-113 14-106 RREJ Field Descriptions ................................................................................................... 14-115 14-107 IGADDRn Field Descriptions........................................................................................... 14-116 14-108 GADDRn Field Descriptions ............................................................................................ 14-116 14-109 FIFOCFG Field Descriptions............................................................................................ 14-117 14-110 ATTR Field Descriptions .................................................................................................. 14-119 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xcii Tables Title Page Number Freescale Semiconductor ...

Page 93

... Signal Encoding for Encoded 8-Bit FIFO......................................................................... 14-159 14-149 Steps for Minimum Register Initialization........................................................................ 14-160 14-150 Custom Preamble Field Descriptions................................................................................ 14-165 14-151 Received Preamble Field Descriptions ............................................................................. 14-166 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number xciii ...

Page 94

... FIFO Interface Mode Signal Configurations ........................................................... 14-232 14-190 8-Bit FIFO Mode Register Initialization Steps ................................................................. 14-233 14-191 SGMII Interface Signal Configuration (4-Wire)............................................................... 14-234 14-192 SGMII Mode Register Initialization Steps........................................................................ 14-234 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xciv Tables Title Page Number Freescale Semiconductor ...

Page 95

... PITARn Field Descriptions ................................................................................................. 16-20 16-12 PIWBAR Field Descriptions............................................................................................... 16-21 16-13 PIWBEAR Field Descriptions ............................................................................................ 16-21 16-14 PIWARn Field Descriptions................................................................................................ 16-22 16-15 ERR_DR Field Descriptions ............................................................................................... 16-24 16-16 ERR_CAP_DR Field Descriptions ..................................................................................... 16-25 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number xcv ...

Page 96

... Power-On Reset Values for Affected Configuration Bits ................................................... 16-68 17-1 POR Parameters for PCI Express Controller ........................................................................ 17-4 17-2 PCI Express Interface Signals—Detailed Signal Descriptions............................................. 17-5 17-3 PCI Express Memory-Mapped Register Map ....................................................................... 17-6 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xcvi Tables Title Page Number Freescale Semiconductor ...

Page 97

... PCI Express Error Capture Register 2 Field Descriptions External Source, Inbound Memory Request Transaction .............................................. 17-41 17-35 PCI Express Error Capture Register 3 Field Descriptions Internal Source, Outbound Transaction.......................................................................... 17-42 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number ...

Page 98

... PCI Express Interrupt Line Register Field Description ...................................................... 17-66 17-74 PCI Express Interrupt Pin Register Field Description ........................................................ 17-66 17-75 PCI Express Bridge Control Register Field Description .................................................... 17-67 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 xcviii Tables Title Page Number Freescale Semiconductor ...

Page 99

... PEX_LTSSM_STAT Status Codes...................................................................................... 17-91 17-112 PEX_GCLK_RATIO Field Descriptions ............................................................................ 17-93 17-113 PEX_PM_TIMER Field Descriptions ................................................................................ 17-94 17-114 PEX_PME_TIMEOUT Field Descriptions ........................................................................ 17-94 17-115 PEX_SSVID_UPDATE Field Descriptions........................................................................ 17-95 17-116 PEX_CFG_READY Field Descriptions ............................................................................. 17-96 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number xcix ...

Page 100

... SNotification Field Descriptions......................................................................................... 19-20 19-17 TransCfg Field Descriptions ............................................................................................... 19-20 19-18 TransStatus Field Descriptions............................................................................................ 19-21 19-19 LinkCfg Field Descriptions................................................................................................. 19-21 19-20 LinkCfg1 Field Descriptions............................................................................................... 19-23 19-21 LinkCfg2 Field Descriptions............................................................................................... 19-23 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev Tables Title Page Number Freescale Semiconductor ...

Page 101

... Relationship Between Command CRC Error and Command Timeout Error for Auto CMD12 ............................................................................................................ 20-32 20-22 HOSTCAPBLT Field Descriptions..................................................................................... 20-33 20-23 WML Field Descriptions .................................................................................................... 20-34 20-24 FEVT Field Descriptions .................................................................................................... 20-35 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number ci ...

Page 102

... PRI_CTRL Register Field Descriptions ............................................................................. 21-38 21-34 SI_CTRL Register Field Descriptions ................................................................................ 21-39 21-35 CONTROL Field Descriptions ........................................................................................... 21-40 21-36 Supported PHY Interfaces .................................................................................................. 21-41 21-37 Typ Field Encodings ........................................................................................................... 21-43 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 cii Tables Title Page Number Freescale Semiconductor ...

Page 103

... Summary Behavior on Host System Errors ...................................................................... 21-116 21-74 Endpoint Capabilities/Characteristics ............................................................................... 21-118 21-75 Current dTD Pointer.......................................................................................................... 21-119 21-76 Multiple Mode Control ..................................................................................................... 21-120 21-77 Next dTD Pointer .............................................................................................................. 21-120 21-78 dTD Token ........................................................................................................................ 21-121 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number ciii ...

Page 104

... PORDEVSR2 Field Descriptions ....................................................................................... 23-13 23-10 GPPORCR Field Descriptions ............................................................................................ 23-14 23-11 GENCFGR Field Descriptions............................................................................................ 23-14 23-12 PMUXCR Field Descriptions ............................................................................................. 23-15 23-13 DEVDISR Field Descriptions ............................................................................................. 23-17 23-14 PMJCR Field Descriptions.................................................................................................. 23-20 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 civ Tables Title Page Number Freescale Semiconductor ...

Page 105

... Watchpoint and Trigger Signals—Detailed Signal Descriptions .......................................... 25-7 25-5 JTAG Test and Other Signals—Detailed Signal Descriptions .............................................. 25-8 25-6 Debug and Watchpoint Monitor Memory Map..................................................................... 25-9 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number ...

Page 106

... PCI Express Controller 1 & 2 Registers ...............................................................................A-11 A-11 GPIO Registers .................................................................................................................... A-15 A-12 SATA Registers .................................................................................................................... A-16 A-13 L2/SRAM Memory-Mapped Registers................................................................................ A-17 0-1 USB Interface Memory Map................................................................................................ A-18 A-2 Module Memory Map .......................................................................................................... A-20 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 cvi Tables Title Page Number Freescale Semiconductor ...

Page 107

... C-3 Host/Agent Configuration (MPC8535E) ................................................................................C-4 C-4 SerDes1 I/O Port Selection (MPC8535E)...............................................................................C-4 C-5 SerDes2 I/O Port Selection (MPC8535E)...............................................................................C-5 C-6 Supported SerDes 1 (PCI Express) Configurations ................................................................C-5 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number cvii ...

Page 108

... Table Number MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 cviii Tables Title Page Number Freescale Semiconductor ...

Page 109

... It is assumed that the reader understands operating systems, microprocessor system design, and the basic principles of RISC processing. Organizations Following is a summary and a brief description of the major parts of this reference manual: Part I, “Overview,” describes the many features of the MPC8536E integrated host processor at an overview level. The following chapters are included: • Chapter 1, “Overview,” ...

Page 110

... L2 cache can also be addressed directly as memory-mapped SRAM. Part III, “Memory, Security, and I/O Interfaces,” defines the memory, security, and I/O interfaces of the MPC8536E and how these blocks interact with one another and with other blocks on the device. The following chapters are included: • ...

Page 111

... Chapter 13, “Enhanced Local Bus Controller,” of the MPC8536E. The main component of the enhanced local bus controller is its memory controller which provides a seamless interface to many types of memory devices and peripherals. The memory controller is responsible for controlling eight memory banks shared by a general-purpose chip-select machine (GPCM), a NAND flash control machine (FCM), and up to three user-programmable machines (UPMs) ...

Page 112

... Part IV, “Global Functions and Debug,” defines other global blocks of the MPC8536E. The following chapters are included: • Chapter 23, “Global Utilities,” management, I/O device enabling, power-on-reset (POR) configuration monitoring, general-purpose I/O signal use, and multiplexing for the interrupt and local bus chip select signals. ...

Page 113

... In some contexts, such as signal encodings, an unitalicized x indicates a don’t care italicized x indicates an alphanumeric variable italicized n indicates a numeric variable. ¬ NOT logical operator & AND logical operator | OR logical operator MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor cxiii ...

Page 114

... Term ADB Allowable disconnect boundary ATMU Address translation and mapping unit BD Buffer descriptor BIST Built-in self test MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 cxiv Section 3.2, “Configuration Signals Sampled at Reset.” Table i. Acronyms and Abbreviated Terms Meaning Freescale Semiconductor ...

Page 115

... IDL Inter-chip digital link IEEE Institute of Electrical and Electronics Engineers IPG Interpacket gap ITLB Instruction translation lookaside buffer IU Integer unit JTAG Joint Test Action Group LAE Local access error MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Meaning cxv ...

Page 116

... Real-time operating system RWITM Read with intent to modify RMW Read modify write Rx Receive RxBD Receive buffer descriptor SCC Serial communication controller SCP Serial control port SDLC Synchronous data link control MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 cxvi Meaning Freescale Semiconductor ...

Page 117

... TSA Time-slot assigner TSEC Three-speed Ethernet controller Tx Transmit TxBD Transmit buffer descriptor UART Universal asynchronous receiver/transmitter UPM User-programmable machine UTP Unshielded twisted pair VA Virtual address ZBT Zero bus turnaround MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Meaning cxvii ...

Page 118

... MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 cxviii Freescale Semiconductor ...

Page 119

... Part I Overview Part I describes the many features of the MPC8536E integrated host processor at an overview level. The following chapters are included: • Chapter 1, “Overview,” MPC8536E integrated host processor. It describes the MPC8536E, its interfaces, and its programming model. The functional operation of the MPC8536E with emphasis on peripheral functions is also described. • ...

Page 120

... MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 I-2 Freescale Semiconductor ...

Page 121

... XOR acceleration, a general-purpose I/O port, and dual universal asynchronous receiver/transmitters (DUART). For high speed interconnect, the MPC8536E provides a set of multiplexed pins that support up to three PCI Express interfaces through a dedicated SerDes. The high level of integration in the MPC8536E helps simplify board design and offers significant bandwidth and performance ...

Page 122

... Hardware support for IEEE Std. 1588™ precision time protocol • Three PCI Express® controllers utilizing the SerDes interface • Two serial ATA interfaces • DDR2/DDR3 SDRAM memory controller MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev Figure 1-1 e500 Core 512-Kbyte 32-Kbyte 32-Kbyte ...

Page 123

... The following sections describe the major functional units of the MPC8536E. 1.3.1 e500 Core and Memory Unit The MPC8536E contains a high-performance 32-bit Book E-enhanced e500v2 core that implements the PowerPC architecture. In addition to 36-bit physical addressing, this version of the e500 core includes: • ...

Page 124

... The local address map is supported by ten local access windows that define mapping within the local 36-bit (64-Gbyte) address space. The MPC8536E can be made part of a larger system address space through the mapping of translation windows. This functionality is included in the address translation and mapping units (ATMUs). Both inbound and outbound translation windows are provided ...

Page 125

... Enhanced Three-Speed Ethernet Controllers (eTSEC) Two MPC8536E on-chip enhanced three-speed Ethernet controllers (eTSECs) incorporate a media access control (MAC) sublayer that supports 10 and 100 Mbps and 1 Gbps Ethernet/802.3 networks with MII, RMII, GMII, RGMII, TBI, and RTBI physical interfaces as well as SGMII interfaces through a dedicated SerDes ...

Page 126

... Support external PHY with UTMI+ low-pin interface (ULPI) 1.3.6.2 Device Mode Operation • Support operation as a stand-alone USB device — Support one upstream facing port — Support six programmable USB endpoints MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev Freescale Semiconductor ...

Page 127

... ENERGY STAR standards. Dynamic power management locally minimizes power consumption in the doze, nap, or sleep modes. Static power is regulated in the deep sleep mode. A jog mode feature is provided on the MPC8536E. In jog mode, the e500 core frequency can be adjusted dynamically while the platform frequency remains unchanged, resulting in optimal device temperature and power dissipation ...

Page 128

... PCI Express Controller The MPC8536E supports a PCI Express interface compliant with the PCI Express Base Specification Revision 1.0a. Each controller is configurable at boot time to act as either root complex or endpoint. The physical layer of the PCI Express interface operates at a 2.5-Gbaud data rate (effective rate of 2 Gbps due to encoding overhead) per lane ...

Page 129

... To chain (both extended and direct) through local memory-mapped chain descriptors. • To handle misaligned transfers, as well as stride transfers and complex transaction chaining. • To specify local attributes such as snoop and L2 write stashing. MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor 2 C, DUART, eLBC Overview ...

Page 130

... Three protocol engines on a per-chip-select basis • Parity support • Default boot ROM chip select with configurable bus width (8, 16 bits) MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev Freescale Semiconductor ...

Page 131

... MPC8536E before being sent to the printer engine. High-speed color processing and concurrency of application in MFP systems require the higher processor performance and fast data movement provided by MPC8536E in order to manipulate large, high-quality images at high speeds. MPC8536E implements advanced power management methods to minimize the power consumption. ...

Page 132

... Network Attached Storage Figure 1-3 illustrates how a network attached storage application can be realized with the MPC8536E. In this application, the MPC8536E PCI Express can be configured for high-speed, 8 lane configuration, which can support high data rate RAID interfaces. For network connectivity, dual Gigabit Ethernet controllers provide high bandwidth to the storage medium ...

Page 133

... MPC8536E in a gaming and information kiosk application. Gaming systems require fast responsive controls and vibrant graphics processing. MPC8536E PCI Express provides the high bandwidth interface to transfer graphics image data and control to the Graphics Processor. Gaming systems are mechanically secure and require low power operation. ...

Page 134

... Network Controller Figure 1-5 illustrates how a network controller application can be realized with the MPC8536E. One of the gigabit Ethernet controllers can be used to interface to an Ethernet switch. The Ethernet interfaces allow the option for SGMII, which provide robust low-power connectivity to PHY devices. MPC8536E also implements IEEE 1588 for network synchronization ...

Page 135

... Table 2-1. PCI PCI Express 2 PCI Express 1 PCI Express 3 Enhanced local bus Configuration space DDR SDRAM MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Table 2-1. Target Interface Codes Source/Target Interface Target Code 00000 00001 00010 00011 00100 ...

Page 136

... Table 2-2 shows one corresponding set of local access window settings. Window 5–9 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 2-2 Example Local Memory Map 0 Memory I/O CCSR Boot ROM PCI Express Figure 2-1. Local Memory Map Example Table 2-2. Local Access Windows Example ...

Page 137

... High-order address bits defining location of the window in the initial address space Window size/attributes Window enable, window size, target interface, and transaction attributes MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Location”). However, note that the e500 core Table 2-3 ...

Page 138

... The local access window registers exist as part of the local access block in the general utilities registers. See Section 2.3.4, “General Utilities Registers.” MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 2-4 Section 2.1, “Local Memory Map Overview and A detailed description of the local access window ...

Page 139

... LAWBAR8—Local access window 8 base address register 0x0_0D10 LAWAR8—Local access window 8 attribute register 0x0_0D28 LAWBAR9—Local access window 9 base address register 0x0_0D30 LAWAR9—Local access window 9 attribute register MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Register Memory Map Access Reset Section/Page ...

Page 140

... Figure 2-3. Local Access IP Block Revision Register 2 (LAIPBRR2) Table 2-6 describes LAIPBRR2 fields. Bits Name 0–7 — Reserved 8–15 IP_INT IP block integration options MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 2-6 Register Figure 15 16 All zeros Table 2-5. LAIPBRR1 Field Descriptions Description Figure ...

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... LAWSR5: 0x0_0CB0 LAWSR11: 0x0_0D70 — W Reset Figure 2-5. Local Access Window n Attributes Registers (LAWAR0–LAWAR7) MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Description 8 BASE_ADDR All zeros Table 2-7. LAWBAR n Field Descriptions Description 11 12 TRGT_ID All zeros Access: Read/Write ...

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... Neither should a new window be used until the effect of the write to the window is visible to all blocks that use the window. This can be guaranteed by completing a read of the last local MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 2-8 Table 2-8. LAWAR n Field Descriptions ...

Page 143

... PCI outbound ATMU windows. The PCI Express interface has four outbound ATMU windows plus a default window. The PCI Express outbound ATMU registers include an extended translation address register so that bits of external MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Memory Map ...

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... The configuration, control, and status window must not overlap a local access window that maps to the DDR controller. Otherwise, undefined behavior occurs. MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 2-10 Section 17.3.5.1, “PCI Express Outbound ATMU Registers” Section 16.3.1.3, “PCI ATMU Inbound for a description of the PCI Express inbound ATMU windows ...

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... Table 2-10. Local Memory Configuration, Control, and Status Register Summary Offset from CCSRBAR 0x0_0000–0x3_FFFF 0x4_0000–0x7_FFFF 0x8_0000–0xB_FFFF 0xC_0000–0xD_FFFF 0xE_0000–0xF_FFFF MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Register Grouping General utilities Programmable interrupt controller (PIC) Reserved Reserved ...

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... MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 2-12 General Utilities Registers Memory Block ...

Page 147

... Reserved bits in the following register descriptions are not guaranteed to have predictable values. Software must preserve the values of reserved bits when writing to a register. Also, when reading from a register, software should not rely on the value of any reserved bit remaining consistent. MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor NOTE ...

Page 148

... Mixed indicates a combination of access types. • Special is used when no other category applies. In this case the register figure and field description table should be read carefully. MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 2-14 0xE 0000 0xE 1000 0xE 2000 0xF FFFC ...

Page 149

... DMA controller 0x2_2000 USB controller 1 0x2_3000 USB controller 2 0x2_4000 eTSEC1 0x2_5000 Reserved MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Table 2-11. CCSR Block Base Address Map Block Section/Page General Utilities (0x0_0000–0x3_FFFF) 16.3/16-11 19.3.1/19-4 19.3.1/19-4 14.5/14-14 Comments 4 ...

Page 150

... Even though it is allocated 64 Kbytes in the memory space, only 8 Kbytes of internal bootrom is physically implemented, and this is located at the upper 8 Kbytes of the allocated 64kbyte address space, from CCSR offset 0xF_E000 to 0xF_FFFF. MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 2-16 Block Section/Page 14 ...

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... Chapter 3 Signal Descriptions This chapter describes the MPC8536E external signals organized into the following sections: • Overview of signals and cross-references for signals that serve multiple functions, including two lists: one by functional block and one alphabetical • List of reset configuration signals • ...

Page 152

... DRAM On-Die Termination MDIC[0:1] Driver impedance calibration MAPAR_ERR DDR address parity in MAPAR_OUT DDR address parity out PCI_AD[31:0] PCI address/data MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 3-2 Table 3-1 lists the signals grouped by Functional Alternate Function(s) Block DDR memory — ...

Page 153

... TSEC1 transmit data 1 TSEC1_TX_EN TSEC1 transmit enable TSEC1_TX_ER TSEC1 transmit error TSEC1_TX_CLK TSEC1 transmit clock in TSEC1_GTX_CLK TSEC1 transmit clock out TSEC1_CRS TSEC1 carrier sense MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Functional Alternate Function(s) Block PCI — PCI — PCI — ...

Page 154

... PULSE_OUT1 TSEC_1588_ IEEE 1588 pulse out 2 PULSE_OUT2 TSEC_1588_ IEEE 1588 alarm out TRIG_OUT[0:1] LAD[0:31] Local bus address/data LDP[0:3] Local bus data parity MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 3-4 Functional Alternate Function(s) Block eTSEC1 FIFO1_TX_FC eTSEC1 FIFO1_RXD[7:0] eTSEC1 FIFO1_RX_DV ...

Page 155

... DMA_DDONE[0:1] DMA done 0–1 DMA_DDONE2 DMA done 2 DMA_DDONE3 DMA done 3 MCP Machine check processor UDE Unconditional debug event IRQ[0:8] External interrupt 0–8 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Functional Alternate Function(s) Block eLBC cfg_cpu_boot eLBC cfg_sys_pll[0:3] eLBC — ...

Page 156

... SerDes2 reference clock, SD2_REF_CLK SerDes2 reference clock complement HRESET Hard reset HRESET_REQ Hard reset request SRESET Soft reset CKSTP_IN Checkstop in MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 3-6 Functional Alternate Function(s) Block PIC DMA_DREQ3 PIC DMA_DACK3 PIC DMA_DDONE3 PIC — ...

Page 157

... USB1 stop USB1_PWRFAULT USB1 power fault USB1_PCTL0 USB1 port control 0 USB1_PCTL1 USB1 port control 1 USB1_CLK USB1 clock USB2_D[7:0] USB2 data MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Functional Alternate Function(s) Block System control — System control TRIG_OUT Power mgmt — ...

Page 158

... General-purpose I/O GPIO7 General-purpose I/O GPIO8 General-purpose I/O GPIO9 General-purpose I/O GPIO[10:11] General-purpose I/O GPIO[12:13] General-purpose I/O GPIO[14:15] General-purpose I/O MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 3-8 Functional Alternate Function(s) Block USB2 — USB2 — USB2 cfg_pci_speed USB2 — ...

Page 159

... Hard reset request 2 IIC1_SCL I C serial clock 2 IIC1_SDA I C serial data 2 IIC2_SCL I C serial clock MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Functional Alternate Function(s) Block Power mgmt — System control — System control — Clock — DMA ...

Page 160

... Local bus PLL synchronization LWE[1:3]/ Local bus write enable LBS[1:3] /byte select 1–3 LWE0/ Local bus write enable LBS0/LFWE /byte select 0 MA[15:0] DDR address MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 3-10 Functional Alternate Function(s) Block — PIC — PIC — ...

Page 161

... PCI clock PCI_DEVSEL PCI device select PCI_FRAME PCI frame PCI_GNT[3:4] PCI grant 3 PCI_GNT0 PCI grant 0 PCI_GNT1 PCI grant 1 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Functional Alternate Function(s) Block DDR memory — DDR memory — DDR memory — ...

Page 162

... SerDes2 reference clock complement SD2_RX[1:0], Receive data, SD2_RX[1:0] receive data complement SD2_TX[1:0], Transmit data, SD2_TX[1:0] transmit data complement SDHC_CD eSDHC MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 3-12 Functional Alternate Function(s) Block PCI cfg_pci_arb PCI — PCI — PCI — ...

Page 163

... TSEC1_COL TSEC1 collision detect TSEC1_CRS TSEC1 carrier sense TSEC1_GTX_CLK TSEC1 transmit clock out TSEC1_RX_CLK TSEC1 receive clock TSEC1_RX_DV TSEC1 receive data valid MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Functional Alternate Function(s) Block eSDHC — eSDHC — eSDHC — ...

Page 164

... TSEC3 transmit data 3 TSEC3_TXD7 TSEC3 transmit data 7 UART_CTS[0:1] DUART clear to send UART_RTS[0:1] DUART ready to send UART_SIN[0:1] DUART serial data in UART_SOUT[0:1] DUART serial data out MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 3-14 Functional Alternate Function(s) Block eTSEC1 FIFO1_RX_ER eTSEC1 FIFO1_RXD[7:0] eTSEC1 FIFO1_TX_CLK ...

Page 165

... HRESET. However, there is a setup and hold time for these signals relative to the rising edge of HRESET, as described in the MPC8536E Integrated Processor Hardware Specifications. Note that the PLL configuration signals have different setup and hold time requirements than the other reset configuration signals ...

Page 166

... For details about all the signals that require external pull-up resistors, see the MPC8536E Integrated Processor Hardware Specifications. Note that the multiplexing of various signals on the MPC8536E is controlled by the PMUXCR register described in Chapter 23, “ ...

Page 167

... USB2 3.3 Output Signal States During Reset When a system reset is recognized (HRESET is asserted), the MPC8536E aborts all current internal and external transactions and releases all bidirectional I/O signals to a high-impedance state. See “Reset, Clocking, and Initialization,” During reset, the MPC8536E ignores most input signals (except for reset configuration signals) and drives most output-only signals to an inactive state ...

Page 168

... PCI Express 2 PCI Express 1/ PCI Express 2/ PCI Express 3 PIC SATA/SGMII SPI USB3 Clock Debug Debug Debug JTAG Power management MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 3-18 Signal MCK[0:5] MCKE[0:3] MCS[0:3] MDM[0:8] MODT[0:3] MRAS MWE UART_RTS[0:1] SDHC_CLK TSEC1_GTX_CLK TSEC1_TX_EN TSEC3_GTX_CLK ...

Page 169

... Table 3-4. Output Signal States During System Reset (continued) Interface Power management System Control System Control MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Signal State During Reset POWER_EN Driven High CKSTP_OUT High-Z HRESET_REQ Input—reset config (test only) ...

Page 170

... Signal Descriptions MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 3-20 Freescale Semiconductor ...

Page 171

... Chapter 4 Reset, Clocking, and Initialization This chapter describes the reset, clocking, and some overall initialization of the MPC8536E, including a definition of the reset configuration signals and the options they select. Additionally, the configuration, control, and status registers are described. Note that other chapters in this book may describe specific aspects of initialization for individual blocks ...

Page 172

... Timing Assertion/Negation—The MPC8536E Integrated Processor Hardware Specifications gives specific timing information for this signal and the reset configuration signals. HRESET_REQ O Hard reset request. Indicates to the board (system in which the MPC8536E is embedded) that a condition requiring the assertion of HRESET has been detected. ...

Page 173

... When the PCI interface is used, SYSCLK also functions as the PCI_CLK signal. Note that this is true whether the device is in agent or host mode. The MPC8536E does not provide a separate PCI_CLK output in host mode. Timing Assertion/Negation—See the MPC8536E Integrated Processor Hardware Specifications for specific timing information for this signal ...

Page 174

... CCSR memory, which begins at offset 0x0 from CCSRBAR. Because CCSRBAR is at offset 0x0 from the beginning of the local access registers, CCSRBAR always points to itself. The contents of CCSRBAR are broadcast internally in the MPC8536E to all functional units that need to be able to identify or create configuration transactions. ...

Page 175

... This prevents problems with incorrect mappings if subsequent configuration of the local access windows uses a different target mapping for the address specified in ALTCBAR. MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor 7 8 ...

Page 176

... Enable second configuration window. Like CCSRBAR, it has a fixed size of 1 Mbyte. 0 Second configuration window is disabled. 1 Second configuration window is enabled. 1–6 — Write reserved, read = 0 MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev BASE_ADDR All zeros Table 4-6. ALTCBAR Bit Settings ...

Page 177

... For systems in which the boot code resides at a different address, the MPC8536E provides boot page translation capability. Boot page translation is controlled by the boot page translation register (BPTR). ...

Page 178

... For more details, see 4.4 Functional Description This section describes the various ways to reset the MPC8536E, the POR configurations, and the clocking on the device. 4.4.1 Reset Operations The MPC8536E has reset input signals for hard and soft reset operation ...

Page 179

... Power-On Reset Sequence The POR sequence for the MPC8536E is as follows: 1. Power is applied to meet the specifications in the MPC8536E Integrated Processor Hardware Specifications. 2. The system asserts HRESET and TRST, causing all registers to be initialized to their default states and most I/O drivers to be three-stated (some clock, clock enabled, and system control signals are active) ...

Page 180

... ASLEEP (High Impedance) 1 READY 1 Multiplexed with TRIG_OUT. MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 4-10 Section 4.4.3.10, “CPU Boot Configuration.” Section 25.3.4.1, “Trigger Out Source Register (TOSR),” Section 25.3.4, “Trigger Out Function.” Section 23.4.1, “Register Descriptions.” ...

Page 181

... System PLL Ratio The system PLL inputs, shown in platform clock used by the MPC8536E. The platform clock, also called the CCB clock, drives the L2 cache, the DDR SDRAM data rate, and the e500 core complex bus (CCB). See “Minimum Frequency Requirements,” for optimal selection of this ratio with regard to available high-speed interface widths and frequencies ...

Page 182

... Section 23.4.1.1, “POR PLL Status Register (PORPLLSR),” described in the PowerPC e500 Core Family Reference Manual and in Integratation Details.” Functional Signals LBCTL, LALE, LGPL2/LOE/LFRE Default (111) MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 4-12 Table 4-9. CCB Clock PLL Ratio Reset Configuration Value Name ...

Page 183

... Functional Reset Configuration Signal Name LGPL1/LFALE cfg_sys_speed Default (1) MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Table 4-11, establish the clock ratio between the DDRCLK input and the Table 4-11. DDR Complex Clock PLL Ratios cfg_ddr_pll[0:2] 000 001 ...

Page 184

... ROM region of the local address map are directed to the interface specified by these inputs. Boot from eSPI or SD/MMC is supported by the MPC8536E using an on-chip ROM which contains the basic eSPI or eSDHC device driver and the code to perform block copy from eSPI EEPROM or SD/MMC card to DDR memory ...

Page 185

... PCI interface. If the device is an agent on the PCI or PCI Express interfaces, then the device is disabled from mastering transactions on that interface until the external host enables so. The external host does this by setting the control registers of the MPC8536E’s interfaces appropriately. See details in the PCI and PCI Express, programming models described in Interface,” ...

Page 186

... MPC8536E acts as an endpoint on PCI Express 1 interface. It acts as the host/root complex for all other PCI/PCI Express interfaces. 110 MPC8536E acts as an agent of an external host on its PCI interface. It acts as a root complex for all PCI Express interfaces. 111 MPC8536E acts as the host processor/root complex on all interfaces (default) ...

Page 187

... The external master frees the CPU to boot by setting EEBPCR[CPU_EN] in the ECM CCB port configuration register (EEBPCR). See Register (EEBPCR),” for more information. MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor on SerDes2 NOTE Blocks.” ...

Page 188

... CPU boot configuration signal described in MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 4-18 Section 23.4.1.2, “POR Boot Mode Status (PBFR).”) and the PCI Express Configuration Ready Register— ...

Page 189

... Table 4-21. Serdes 2 Reference Clock Configuration Functional Reset Configuration Signal Name TSEC3_TXD3, cfg_srds2_ref_clk[0:1] TSEC_1588_ PULSE_OUT2 Default (11) MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Table 4-20 describes the configuration of the DDR Table 4-20. DDR DRAM Type Value (Binary) 0 DDR3 1.5 V, CKE low at reset ...

Page 190

... Default (1) The value of this configuration setting does not affect the width of the FIFO interface on eTSEC3, which is always 8 bits. MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 4-20 Table 4-22, selects standard versus reduced width for three-speed Table 4-22. eTSEC1 Width Configuration ...

Page 191

... PORDEVSR (POR device status register) described in Status Register (PORDEVSR).” Reset Configuration Functional Signal Name TSEC3_TXD[0:1] cfg_tsec3_prtcl[0:1] Default (11) MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor Table 4-24, select the protocol (FIFO, MII, GMII or TBI) used by Table 4-24. eTSEC1 Protocol Configuration Value (Binary) 00 The eTSEC1 controller operates using 8-bit FIFO protocol ...

Page 192

... PORIMPSCR, described in Register (PORIMPSCR).” Reset Configuration Functional Signal Name PCI_GNT1 cfg_pci_impd Default (1) MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 4-22 Table 4-26, specify the clock mode (synchronous or asynchronous) Section 4.4.4.1, “System Clock/PCI Clock/DDR Table 4-26. PCI Clock Select Value (Binary) 0 Asynchronous mode ...

Page 193

... DDR SDRAM source ID field and data valid strobe are driven onto the ECC pins. ECC checking and generation are disabled in this case. ECC signals driven from the SDRAMs must be electrically disconnected from the ECC I/O pins of the MPC8536E in this mode. Functional ...

Page 194

... System Clock/PCI Clock/DDR Clock The MPC8536E takes a single input clock, SYSCLK, as its primary clock source for the e500 core and all of the devices and interfaces that operate synchronously with the core. As shown in SYSCLK input (frequency) is multiplied up using a phase lock loop (PLL) to create the core complex bus (CCB) clock (also called the platform clock) ...

Page 195

... PCI Express and SGMII Clocks Clocks for these high speed interfaces on the MPC8536E are derived from a PLL in the SerDes block. This PLL is driven by a reference clock (SDn_REF_CLK/SDn_REF_CLK) whose input frequency is a function of the protocol and bit rate being used as shown in ...

Page 196

... RTC can also be used (optionally) by the programmable interrupt controller (PIC) global timer facilities. The RTC is separate from the e500 core clock and is intended to support relatively low frequency timing applications. The RTC frequency range is specified in the MPC8536E Integrated Processor Hardware Specifications, but the maximum value should not exceed one-quarter of the CCB Frequency. ...

Page 197

... Boot 4.5.1.1.1 Overview The MPC8536E is capable of loading initialization code from a memory device that is connected to the eSDHC controller interface. This device can be either MMC card or other variants compatible with these devices. The term SD/MMC will be used when referring to the memory device. ...

Page 198

... Initial setting will use a serial clock below 400 kHz; the SD/MMC internal registers are read by initialization code and parsed to determine the optimal clock frequency supported by the SD/MMC card inserted. • High speed cards are supported (up to 50MHz SD and 52MHz MMC). MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 4-28 Freescale Semiconductor ...

Page 199

... BOOT signature, it means that the SD/MMC card doesn't contain a valid user code. In such case the boot loader code will disable the eSDHC and will issue a hardware reset request of the SoC by setting RSTCR[HRESET_REQ]. 0x44–0x47 Reserved MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 Freescale Semiconductor 0x00 Reserved 0x3F ...

Page 200

... Config Data N (final Config Data N optional) 8*(N–1)+4 User’s code. Note that user's code must start on a 512-byte boundary <=40 if compatibility with FAT12/FAT16/FAT32 filesystems is required. Refer to FAT12/FAT16/FAT32 Filesystems” for details. MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1 4-30 Data Bits [0:31] ... Section , “ ...