MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1384

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
21.5.4.4
DWords 4 and 5 are the data buffer page pointers for the transfer. This structure supports one physical page
cross. The most-significant 20 bits of each DWord in this section are the 4K (page) aligned buffer pointers.
The least-significant 12 bits of each DWord are used as additional transfer state.
21-50
31–12
11–0
Bits
Bits
7–0
Current Offset
Buffer Pointer
(Page 0)
Name
Status
Name
siTD Buffer Pointer List (Plus)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
This field records the status of the transaction executed by the host controller for this slot. This field is
a bit vector with the following encoding:
Bits 31–12 are 4K page-aligned, physical memory addresses. These bits correspond to physical
address bits 31–12 respectively. The field P specifies the current active pointer
The 12 least-significant bits of the Page 0 pointer is the current byte offset for the current page
pointer (as selected with the page indicator bit (P field)). The host controller is not required to write
this field back when the siTD is retired (Active bit transitioned from a one to a zero).
Status Bits
Table 21-47. siTD Transfer Status and Control (continued)
7
6
5
4
3
2
1
0
Table 21-48. siTD Buffer Pointer Page 0 (Plus)
Active. Set by software to enable the execution of an isochronous split transaction
by the host controller.
ERR. Set by the host controller when an ERR response is received from the
companion controller.
Data buffer error. Set by the host controller during status update to indicate that the
host controller is unable to keep up with the reception of incoming data (overrun) or
is unable to supply data fast enough during transmission (under run). In the case of
an under run, the host controller will transmit an incorrect CRC (thus invalidating
the data at the endpoint). If an overrun condition occurs, no action is necessary.
Babble detected. Set by the host controller during status update when” babble” is
detected during the transaction generated by this descriptor.
Transaction error (XactErr). Set by the host controller during status update in the
case where the host did not receive a valid response from the device (Time-out,
CRC, Bad PID, etc.). This bit will only be set for IN transactions.
Missed micro-frame. The host controller detected that a host-induced hold- off
caused the host controller to miss a required complete-split transaction.
Split transaction state (SplitXstate). The bit encodings are:
0 Do start split. This value directs the host controller to issue a Start split
1 Do complete split. This value directs the host controller to issue a Complete split
Reserved, should be cleared. Bit reserved for future use and should be cleared.
transaction to the endpoint when a match is encountered in the S-mask.
transaction to the endpoint when a match is encountered in the C-mask.
Description
Description
Definition
Freescale Semiconductor