MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 686

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Local Bus Controller
latch uses this signal to capture the address and provide it to the address pins of the memory or peripheral
device. When LALE is negated, LAD then serves as the (bi-directional) data bus for the access. Any
address phase initiates the assertion of LALE, which has a programmable duration of between 1 and 4 bus
clock cycles.
To ensure adequate hold time on the external address latch, LALE negates earlier than the address changes
on LAD during address phases. By default, LALE negates earlier by 1 platform clock period. For example,
if the platform clock is operating at 533 MHz, then 1.8 ns of address hold time is introduced. However, at
higher frequencies, the duration of the shortened LALE pulse may not meet the minimum latch enable
pulse width specifications of some latches. In such cases, setting LBCR[AHD] = 1 increases the LALE
pulse width by ½ platform clock cycle, but decreases the address hold time by the same amount. If both
longer hold time and longer LALE pulse duration are needed, then the address phase can be extended using
the ORn[EAD] and LCRR[EADC] fields, and the LBCR[AHD] bit can be left at 0. However, this will add
latency to all address tenures.
The frequency of LALE assertion varies across the three memory controllers:
In general, when using the GPCM controller it is not necessary to use LA if a sufficiently wide latch is
used to capture the entire address during LALE phases. The UPMs may require LA if the eLBC is
generating its own burst address sequence.
To illustrate how a large transaction is handled by the eLBC,
GPCM performing a 32-byte write starting at address 0x5420. Note that during each of the 32 assertions
of LALE, LA[27:31] exactly mirror LAD[27:31], but during data phases, only LAD[0:7] and LDP[0] are
driven with valid data and parity, respectively.
13-44
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For GPCM, every assertion of LCSn is considered an independent access, and accordingly, LALE
asserts prior to each such access. For example, GPCM driving an 8-bit port would assert LALE and
LCSn 32 times in order to satisfy a 32-byte cache line transfer.
For FCM, LALE asserts prior to each multi-command operation sequence, but LALE can be
ignored on NAND Flash EEPROM accesses as the signal does not enable address latching in such
devices. The value on the LAD and LA pins during LALE assertion is driven low-impedance, but
otherwise not defined for FCM banks.
In the case of UPM, the frequency of LALE assertion depends on how the UPM RAM is
programmed. UPM single accesses typically assert LALE once, upon commencement, but it is
possible to program UPM to assert LALE several times, and to change the values of LAn with and
without LALE being involved.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 13-30
shows eLBC signals for the
Freescale Semiconductor