MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 275

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MPC8536E-ANDROID

Manufacturer Part Number
MPC8536E-ANDROID
Description
HARDWARE/SOFTWARE ANDROID OS
Manufacturer
Freescale Semiconductor
Series
PowerQUICC ™r
Type
MPUr

Specifications of MPC8536E-ANDROID

Contents
Board
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Chapter 8
DDR Memory Controller
8.1
The fully programmable DDR SDRAM controller supports most JEDEC standard x8, x16, or x32 DDR2
and DDR3 memories available. In addition, unbuffered and registered DIMMs are supported. However,
mixing different memory types or unbuffered and registered DIMMs in the same system is not supported.
Built-in error checking and correction (ECC) ensures very low bit-error rates for reliable high-frequency
operation. Dynamic power management and auto-precharge modes simplify memory system design. A
large set of special features, including ECC error injection, support rapid system debug.
Freescale Semiconductor
Introduction
In this chapter, the word ‘bank’ refers to a physical bank specified by a chip
select; ‘logical bank’ refers to one of the four or eight sub-banks in each
SDRAM chip. A sub-bank is specified by the 2 or 3 bits on the bank address
(MBA) pins during a memory access.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
NOTE
8-1

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