MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 297

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
19–21 WR_DATA_DELAY Write command to write data strobe timing adjustment. Controls the amount of delay applied to the
23–25
26–31
8.4.1.8
The DDR SDRAM control configuration register, shown in
specifies certain operating features such as self refreshing, error checking and correcting, registered
DIMMs, and dynamic power management.
Freescale Semiconductor
Offset 0x110
Reset
Reset
Bits
22
For CPO decodings other than 00000 and 11111, ‘READ_LAT’ is rounded up to the next integer value.
W
W
R
R
MEM_EN SREN ECC_EN RD_EN — SDRAM_TYPE
2T_EN
FOUR_ACT
16
0
0
CKE_PLS
Name
DDR SDRAM Control Configuration (DDR_SDRAM_CFG)
—
Figure 8-9. DDR SDRAM Control Configuration Register (DDR_SDRAM_CFG)
17
0
1
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 8-12. TIMING_CFG_2 Field Descriptions (continued)
data and data strobes for writes. See
details. The write preamble typically is driven high for 1/2 DRAM cycle, and then it is driven low for
1/2 DRAM cycle. However, for WR_DATA_DELAY settings of 0 clocks and 1/4 clocks, the write
preamble is driven low for the entire DRAM cycle. If the preamble needs to switch high first (to meet
DDR3 specifications), then these values should not be used.
000 0 clock delay
001 1/4 clock delay
010 1/2 clock delay
011 3/4 clock delay
Reserved
Minimum CKE pulse width (t
000 Reserved
001 1 clock
010 2 clocks
011 3 clocks
Window for four activates (t
000000 Reserved
000001 1 cycle
000010 2 cycles
000011 3 cycles
000100 4 cycles
0
2
BA_INTLV_CTL
0
3
0
4
0
5
1
FAW
CKE
). This is applied to DDR2/DDR3 with eight logical banks only.
).
23
1
7
All zeros
24 25
0 0
8
Section 8.5.7, “DDR SDRAM Write Timing Adjustments,”
—
—
9
100 1 clock delay
101 5/4 clock delay
110 3/2 clock delay
111 Reserved
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks
...
011110 30 cycles
011111 31 cycles
100000 32 cycles
100001–111111 Reserved
Description
DYN_PWR
Figure
x32_EN
10
26
0
8-9, enables the interface logic and
PCHB8 HSE
11
27
0
DBW
12
28
0
8_BE
—
13
29
0
DDR Memory Controller
Access: Read/Write
MEM_HALT
NCAP
14
30
0
3T_
8-23
EN
BI
15
31
0
for