MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1489

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22.3.6
The GPIO interrupt control register (GPICR), shown in
corresponding port line asserts an interrupt request on either a high-to-low change or any change on the
state of the signal.
Table 22-8
Freescale Semiconductor
0–31
0–31
Bits
Bits
Offset 0xC14
Reset
W
R
Name
Name
0
D n
D n
defines the bit fields of GPICR.
GPIO Interrupt Control Register (GPICR)
Interrupt mask. Indicates whether an interrupt event is masked or not masked. Bits D0–D15 correspond to
signals GPIO[0:15]. Bits D16–D31 are unused.
0 The input interrupt signal is masked (disabled).
1 The input interrupt signal is not masked (enabled).
Edge detection mode. Bits D0–D15 correspond to signals GPIO[0:15]. Bits D16–D31 are unused. The
corresponding port line asserts an interrupt request according to the following:
0 Any change on the state of the port generates an interrupt request.
1 High-to-low change on the port generates an interrupt request.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 22-7. GPIO Interrupt Control Register (GPICR)
Table 22-7. GPIMR Bit Settings
Table 22-8. GPICR Bit Settings
All zeros
Description
Description
D n
Figure
22-7, determines whether the
General Purpose I/O (GPIO)
Access: Read/write
22-5
31