MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 984

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14-236
Other information about the link is also returned. (Extend Status, No pre, Remote Fault, An Ability, Link status, extend Ability)
This enables the TBI to restart Auto-Negotiations using the configuration set in the AN Advertisement register.
Set up the MII Mgmt for a read cycle to PHY MII Mgmt register (write the PHY address and Register address),
read the MII Mgmt AN Link Partner Base Page Ability register and check bits 9 and 10. (Half and Full Duplex)
MII Mgmt AN Link Partner Base Page Ability ---> [0000_0000_0000_0000_0000_000x_1110_0000]
read the MII Mgmt AN Expansion register and check bits 13 and 14 (NP Able and Page Rx’d)
The PHY Status control register is at address 0x1 and in this case the PHY Address is 0x10.
Perform an MII Mgmt read cycle of AN Link Partner Base Page Ability Register. (Optional)
(Uses the PHY address (0x10) and Register address (6) placed in MIIMADD register),
(Uses the PHY address (0x10) and Register address (5) placed in MIIMADD register),
(Uses the PHY address (2) and Register address (2) placed in MIIMADD register),
MII Mgmt AN Expansion ---> [0000_0000_0000_0000_0000_0000_0000_0110]
MII Mgmt AN Expansion ---> [0000_0000_0000_0000_0000_0000_0000_0110]
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 14-192. SGMII Mode Register Initialization Steps (continued)
Writing to MII Mgmt Control with 16-bit data intended for TBI’s Control register,
Setup MIIMADD[0000_0000_0000_0000_0001_0000_0000_0110]
Setup MIIMADD[0000_0000_0000_0000_0001_0000_0000_0101]
MACnADDR1/2[0000_0000_0000_0000_0000_0000_0000_0000]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
DMACTRL[0000_0000_0000_0000_0000_0000_0000_0000]
MIIMCON[0000_0000_0000_0000_0001_0011_0100_0000]
MIIMADD[0000_0000_0000_0000_0001_0000_0000_0001]
GADDR n [0000_0000_0000_0000_0000_0000_0000_0000]
Perform an MII Mgmt read cycle of AN Expansion Register.
IEVENT[0000_0000_0000_0000_0000_0000_0000_0000]
RCTRL[0000_0000_0000_0000_0000_0000_0000_0000]
IMASK[0000_0000_0000_0000_0000_0000_0000_0000]
Read MII Mgmt Indicator register and check for Busy = 0,
read the MIIMSTAT register and check bit 10 (AN Done)
Check to see if PHY has completed Auto-Negotiation.
Perform an MII Mgmt read cycle of Status Register.
This indicates that the write cycle was completed.
Check to see if MII Mgmt write is complete.
Perform an MII Mgmt write cycle to TBI.
Initialize MACnADDR1/2 (Optional)
Initialize DMACTRL (Optional)
Clear MIIMCOM[Read Cycle]
Clear MIIMCOM[Read Cycle]
Clear MIIMCOM[Read Cycle]
Initialize GADDR n (Optional)
Set MIIMCOM[Read Cycle]
When MIIMIND[BUSY] = 0,
Set MIIMCOM[Read Cycle]
When MIIMIND[BUSY] = 0,
Set MIIMCOM[Read Cycle]
When MIIMIND[BUSY] = 0,
Initialize RCTRL (Optional)
Initialize IMASK (Optional)
Clear IEVENT register,
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