MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1043

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.3.1.2.3
The PCI outbound window base address registers (POWBARn) point to the beginning of each translation
window in the local 32-bit address space. Addresses for outbound transactions are compared to the
appropriate bits in these registers, according to the sizes of the windows. If a transaction does not fall
within one of these windows, the default translation and mapping is used. The default window is always
enabled and used when the other windows miss.
Note that POWBAR0 (for outbound ATMU window 0) is not used, because window 0 is the default
window used when no other windows match. POWBAR0 may be read from and written to, but the value
is ignored.
The format of the POWBARn is shown in
Table 16-9
16.3.1.2.4
The PCI outbound window attributes registers (POWARn) define the window sizes to translate and other
attributes for the translations. The minimum window size is 4 Kbytes. The maximum window size is 16
Gbytes.
The default window attribute register, POWAR0, is shown in
POWARn registers are the same, only the reset values are different.
Freescale Semiconductor
Offset 0xC28, 0xC48, 0xC68, 0xC88
Reset
12–31 WBA Window base address. Source address which is the starting point for the outbound window.
0–11 WBEA Window base extended address. Bits 0–7 are reserved; bits 8–11 correspond to bits [0:3] of the
W
Bits
R
12–31
0–11
Bits
0
Name
describes the field of the POWBARn.
Name
PCI Outbound Window Base Address Registers (POWBAR n )
PCI Outbound Window Attributes Registers (POWAR n )
TEA
—
Figure 16-8. PCI Outbound Window Base Address Registers (POWBAR n )
(internal platform) base address.
0x000 – 0x00F are valid.
0x010 and greater are reserved.
The specified address must be aligned to the window size, as defined by POWAR n [OWS]. Corresponds
to bits [4-35] of the (internal platform) base address.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved
Translation extended address. Comprise bits [63:44] of the translation address.
WBEA
Table 16-9. POWBAR n Field Descriptions
Table 16-8. POTEAR n Field Descriptions
11 12
Figure
16-8.
All zeros
Description
Description
Figure
16-9. Note that the fields for all of the
WBA
Access: Read/Write
PCI Bus Interface
16-17
31