MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 295

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.4.1.7
DDR SDRAM timing configuration 2, shown in
Freescale Semiconductor
Offset 0x10C
16–19
20–23
25–27 ACTTOACT Activate-to-activate interval (t
29–31 WRTORD Last write data pair to read command issue interval (t
Reset
Bits
24
28
W
R
0
REFREC
WRREC
ADD_LAT
Name
—
—
DDR SDRAM Timing Configuration 2 (TIMING_CFG_2)
Figure 8-8. DDR SDRAM Timing Configuration 2 Register (TIMING_CFG_2)
Refresh recovery time (t
command is allowed. This field is concatenated with TIMING_CFG_3[EXTREFREC] to obtain a 7-bit value
for the total refresh recovery. Note that hardware adds an additional 8 clock cycles to the final, 7-bit value
of the refresh recovery, such that t
0000 8 clocks
0001 9 clocks
0010 10 clocks
Last data to precharge minimum interval (t
associated with a write command until a precharge command is allowed. If
DDR_SDRAM_CFG_2[OBC_CFG] is set, then this field needs to be programmed to (t
0000 Reserved
0001 1 clock
0010 2 clocks
0011 3 clocks
0100 4 clocks
0101 5 clocks
0110 6 clocks
0111 7 clocks
Reserved, should be cleared.
activate command is allowed for a different logical bank in the same physical bank (chip select).
000 Reserved
001 1 clock
010 2 clocks
011 3 clocks
Reserved, should be cleared.
data pair and the subsequent read command to the same physical bank. If
DDR_SDRAM_CFG_2[OBC_CFG] is set, then this field needs to be programmed to (t
000 Reserved
001 1 clock
010 2 clocks
011 3 clocks
3 4
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
CPO
Table 8-11. TIMING_CFG_1 Field Descriptions (continued)
8 9
WR_LAT
RFC
12 13
). Controls the number of clock cycles from a refresh command until an activate
RRD
0011 11 clocks
…
1111 23 clocks
1000 8 clocks
1001 9 clocks
1010 10 clocks
1011 11 clocks
1100 12 clocks
1101 13 clocks
1110 14 clocks
1111 15 clocks
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks
—
). Number of clock cycles from an activate command until another
RFC
15 16
Figure
is calculated as follows: t
RD_TO_PRE WR_DATA_DELAY — CKE_PLS
All zeros
WR
). Determines the number of clock cycles from the last data
Description
8-8, sets the clock delay to data for writes.
18
WTR
19
). Number of clock cycles between the last write
RFC
= {EXT_REFREC || REFREC} + 8.
21 22 23
DDR Memory Controller
Access: Read/Write
25 26
WR
WTR
+ 2 cycles).
+ 2 cycles).
FOUR_ACT
8-21
31