MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1338

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
21.2.2
The USBn_CLK input provides the clocking signal for the ULPI PHY interface. The clock is 60 MHz.
Detailed clock specifications are given in the appropriate hardware specifications document.
21.3
This section provides the memory map and detailed descriptions of all USB interface registers.
Table 21-2
name, and a cross-reference to the complete description of each register. Note that the full register address
is comprised of CCSRBAR together with the USB controller block base address and offset listed in
Table
21-4
0x000–0x0FF
Offset
0x100
0x102
0x104
0x108
0x120
0x124
0x140
0x144
0x148
USB n _D[7:0]
21-2. Undefined 4-byte address spaces within offset 0x000–0xFFF are reserved.
Signal
Memory Map/Register Definitions
shows the memory mapped registers of the USB controllers and their offsets. It lists the offset,
PHY Clocks
A write to registers in the USB controller memory map may cause the
system to hang if PORTSC[PHCD]=0 when no USB PHY clock is applied.
Reserved, should be cleared
CAPLENGTH—Capability register length
HCIVERSION—Host interface version number
HCSPARAMS—Host crtl. structural parameters
HCCPARAMS—Host crtl. capability parameters
DCIVERSION—Device interface version number
DCCPARAMS—Device controller parameters
USBCMD—USB command
USBSTS—USB status
USBINTR—USB interrupt enable
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
I/O
I/O Data bit n . USB n _D n is bit n of the 8-bit (USB n _D7–USB n _D0), uni-directional data bus used
to carry USB, register, and interrupt data between the PHY and the USB controller.
Meaning
Table 21-1. ULPI Signal Descriptions (continued)
Timing Synchronous to PHY_CLK.
USB Controller 3—Block Base Address 0x2_B000
USB Controller 1—Block Base Address 0x2_2000
USB Controller 2—Block Base Address 0x2_3000
State
Table 21-2. USB Interface Memory Map
Register
Asserted—Data bit n is 1.
Negated—Data bit n is 0.
USB Controller 1 Registers
NOTE
Description
Access
Mixed
Mixed
R/W
—
R
R
R
R
R
R
0x0008_ n B00
0x0111_0011
0x0000_0006
0x0000_0186
0x0000_00 n 0
0x0000_0000
0x0100
0x0001
Reset
0x40
—
Freescale Semiconductor
21.3.1.6/2121-10
21.3.2.1/2121-11
21.3.2.2/2121-13
21.3.2.3/2121-15
21.3.1.1/2121-7
21.3.1.2/2121-7
21.3.1.3/2121-7
21.3.1.4/2121-8
21.3.1.5/2121-9
Section/Page
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