MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 14

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
10.3.1
10.3.2
10.3.2.1
10.3.2.2
10.3.3
10.3.4
10.3.4.1
10.3.5
10.4
10.4.1
10.4.1.1
10.4.1.2
10.4.1.3
10.4.2
10.4.2.1
10.4.2.2
10.4.3
10.4.3.1
10.4.3.1.1
10.4.3.1.2
10.4.3.1.3
10.4.3.1.4
10.4.4
10.4.4.1
10.4.4.2
10.4.4.3
10.4.4.4
10.4.5
10.4.5.1
10.4.5.2
10.5
10.5.1
10.5.1.1
10.5.1.2
10.5.1.2.1
10.5.1.2.2
10.5.2
10.5.2.1
10.5.2.2
10.5.3
10.5.3.1
xiv
Polychannel.................................................................................................................. 10-32
Controller ..................................................................................................................... 10-46
Descriptor Structure ................................................................................................. 10-20
Descriptor Format: Header Dword .......................................................................... 10-20
Descriptor Format: Pointer Dwords......................................................................... 10-25
Link Table Format ................................................................................................... 10-26
Descriptor Types ...................................................................................................... 10-30
Channel Operation ................................................................................................... 10-32
Channel Interrupts.................................................................................................... 10-34
Polychannel Registers.............................................................................................. 10-35
Channel Registers .................................................................................................... 10-37
Channel Buffers and Tables ..................................................................................... 10-45
Bus Transfers ........................................................................................................... 10-46
Arbitration Algorithms ............................................................................................ 10-48
Controller Interrupts ................................................................................................ 10-49
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Selecting Execution Units—EU_SEL0 and EU_SEL1 ....................................... 10-22
Selecting Descriptor Type—DESC_TYPE ......................................................... 10-23
Example of Link Table Operation ....................................................................... 10-29
Channel Descriptor Processing............................................................................ 10-32
Channel Arbitration ............................................................................................. 10-33
Channel Host Notification ................................................................................... 10-34
Channel Done Interrupt ....................................................................................... 10-35
Channel Error Interrupt........................................................................................ 10-35
Traffic Counters ................................................................................................... 10-35
Channel Configuration Register (CCR)............................................................... 10-37
Channel Status Register (CSR)............................................................................ 10-41
Current Descriptor Pointer Register (CDPR) ...................................................... 10-43
Fetch FIFO Enqueue Register (FFER) ................................................................ 10-44
Descriptor Buffer (DB)........................................................................................ 10-45
Scatter and Gather Link Tables (SLT, GLT) ........................................................ 10-45
Host-Controlled Access ....................................................................................... 10-46
Channel-Controlled Access ................................................................................. 10-47
Round-Robin Arbitration..................................................................................... 10-48
Weighted Priority Arbitration .............................................................................. 10-48
Controller Interrupt Conditions and Interrupt Generation................................... 10-49
Fetch FIFO Enqueue Counter.......................................................................... 10-35
Descriptor Finished Counter............................................................................ 10-36
Data Bytes In Counter ..................................................................................... 10-36
Data Bytes Out Counter................................................................................... 10-37
Channel Controlled Read—Detailed Description ........................................... 10-47
System Bus Master Write—Detailed Description ........................................... 10-48
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Freescale Semiconductor
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