MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 548

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
software performs host-controlled register accesses only on a few registers for initial configuration and
error handling.
This execution unit (EU) includes an ICVchecking feature, which means it can generate an ICV and
compare it to another supplied ICV. The pass/fail result of this ICV check can be returned to the host either
through interrupt or by using a writeback of EU status fields into the host memory, but not using both
methods at the same time.
To signal the ICV checking result by status writeback, turn on either the IWSE bit or AWSE bit in the
channel configuration register (for more information, see
Register
Mask Register
undisturbed.
To signal the ICV checking result by interrupt, unmask the ICE bit in the interrupt mask register and turn
off the IWSE and AWSE bits in the channel configuration register. If there is no ICV mismatch, the normal
DONE signal (by interrupt or writeback) occurs. When there is an ICV mismatch, there is an ERROR
interrupt signal to the host, but no DONE interrupt signal or writeback.
10.7.5.1
The KEU mode register, shown in
The mode register is cleared when the KEU is reset or re-initialized. Setting a reserved mode bit generates
a data error. Setting both the GSM and EDGE bits to one generates a data error. If the KEU mode register
is modified during processing, a context error is generated.
Table 10-53
10-118
Offset 0x3_E000
Reset
0–55
Bits
56
W
R
0
Name
GSM
(CCR)”), and mask the ICE bit in the interrupt mask register
—
describes the KEU mode register fields.
KEU Mode Register (KEUMR)
Reserved
Select GSM A5/3 blocks
0 GSM A5/3 blocks not selected
1 GSM A5/3 blocks selected
Note 1: For GSM A5/3, Two 114-bit blocks are required to be produced each 4.615mS slot. If GSM = 1, the first
Note 2: If GSM = 0, 228 contiguous bits may be read with successive reads of the output FIFO. In this case the
Note 3: If GSM is set to 1, while EDGE = 1, an interrupt/error is generated.
(KEUIMR)”). In this case the normal DONE signal (by interrupt or writeback) is
read of the output FIFO retrieves the first 64 bits of block 1. The second read of the output FIFO retrieves
the next 50 bits of block 1 (the remaining bits of this 64-bit word are cleared to zero). The third read of the
output FIFO retrieves the first 64 bits of block 2, while a fourth read of the output FIFO retrieves the next 50
bits of block 2 (the remaining bits of this 64-bit word are cleared to zero).
host (application) is responsible for handling the A5/3 block formatting.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 10-53. KEU Mode Register Field Descriptions
Figure
Figure 10-64. KEU Mode Register
—
10-64, contains several bits which are used to program the KEU.
All zeros
Description
Section 10.4.4.1, “Channel Configuration
55
(Section 10.7.5.7, “KEU Interrupt
GSM CICV EDGE PE INT — ALG
56
57
Freescale Semiconductor
58
Access: Read/Write
59
60
61 62 63