MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 351

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 8-53
code; the second corresponds to SDMODE. The Mode Register Set cycle time is set to 2 DRAM cycles.
8.5.6
To reduce loading, registered DIMMs latch the DDR SDRAM control signals internally before using them
to access the array. Setting DDR_SDRAM_CFG[RD_EN] compensates for this delay on the DIMMs’
control bus by delaying the data and data mask writes (on SDRAM buses) by an extra SDRAM clock
cycle.
Freescale Semiconductor
SDRAM Clock
DDR SDRAM Registered DIMM Mode
shows the timing of the mode-set command. The first transfer corresponds to the ESDMODE
Application system board must assert the reset signal on DDR memory
devices until software is able to program the DDR memory controller
configuration registers, and must deassert the reset signal on DDR memory
devices before DDR_SDRAM_CFG[MEM_EN] is set. This ensures that
the DDR memory devices are held in reset until a stable clock is provided
and, further, that a stable clock is provided before memory devices are
released from reset.
MDQ n
MRAS
MCAS
MDQS
MBA n
MWE
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
MCS
MA n
Figure 8-53. DDR SDRAM Mode-Set Command Timing
Code
0x4
0
1
Code
0x0
2
3
4
NOTE
5
6
7
8
9
10
11
DDR Memory Controller
12
8-77