MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1551

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Global Utilities
23.5.1.14.5 eTSEC Wake-on-LAN—ARP (User Defined) Packet
The eTSEC can generate a wake-up event upon detecting an ARP (user defined) packet. Prior to entering
sleep or deep sleep, the user needs to configure the wake-up packet header fields in the Ethernet controller
parser. The eTSEC should also be configured to generate an interrupt when the ARP (user defined) packet
is received.
Additionally, the user should clear the Magic packet enable bit in the Ethernet controller
(MACCFG2[MPEN]) and the eTSEC clock disable bit in the PMCDR register (PMCDR[TSECx] = 0).
The eTSEC generates an interrupt upon detecting the ARP packet only after the last RxBD packet is closed
and data is stored in the external memory.
In general the user may wish to configure the interrupt controller to enable both the eTSEC receive
interrupt (which will be generated when an ARP packet is received), and the eTSEC error interrupt (which
may be generated in an error situation). It is the user’s responsibility to determine for their system which
error interrupts should be masked, and which are critical errors that should be used as wakeup events.
While in this low-power mode, the eTSEC may continue to issue transactions to DDR. The user should set
DDR_SR_CNTR[SR_IT] to a non-zero value, and ensure that DDR_SDRAM_CFG[SREN] = 1. This
causes the DDR to enter self refresh mode after being idle for an user defined number of DDR clock cycles.
Optionally, the user through software can decide keep the DDR always ON instead of in self refresh mode.
Note that using this method requires the user to configure the Ethernet controller filer to reject all kind of
Ethernet frames beside the ARP (user-defined) packet; otherwise the DDR will exit self refresh although
no ARP (user-defined) packet has been received.
After an ARP (user-defined) packet is received, the eTSEC remains in ARP (user-defined) packet filing
mode, and packets of other types will be dropped until software changes the eTSEC filing rules to accept
other packets for normal operation. Note that in the time between receiving the ARP (user-defined) packet,
and the time when software re-enables the eTSEC normal operation, multiple ARP (user-defined) packets
may be received.
23.5.1.15 External Power Supply Control
The following diagrams shows the assumed scenarios for controlling the power supply to the MPC8356E.
An external source is required to switch off the CORE_VDD and CORE_AVDD supplies in low power
mode. A commercial power switch can be used but there is usually a switching delay associated with these
devices, sometimes around 1ms.
The target is to get an equal voltage on CORE_VDD/CORE_AVDD and PLAT_VDD/PLAT_AVDD
supplies. It is done by using a FET transistor on the line of PLAT_VDD/PLAT_AVDD supplies that
are“always on”. by this we get a same IR drop on CORE_VDD/CORE_AVDD and
PLAT_VDD/PLAT_AVDD. The PMC is open/close the FET transistor by a power enable command so a
voltage to the right blocks is given or not given.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Freescale Semiconductor
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