MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 373

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
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Support for the following interrupt sources:
— External—Off-chip signals, IRQ[0:11]
— Internal—These are on-chip sources from peripheral logic within the integrated device
Interrupts generated from within the PIC itself, which are as follows:
— Global timers A and B internal to the PIC
— Interprocessor interrupts (IPI)—Intended for communication between different processor
— Message registers—From within the PIC. Triggered on register write, cleared on read. Used for
— Shared message signaled registers—From within the PIC. Triggered on register write, cleared
Three types of programmable interrupt outputs:
— External interrupt (int). Any of the PIC interrupt sources can be programmed to direct interrupt
— Critical interrupt (cint). Connected to the respective core’s critical interrupt input.
— IRQ_OUT.
Programming model compliant with the OpenPIC architecture.
— Message, interprocessor and global timer interrupts. (Note that the interprocessor and global
— The following OpenPIC-defined features support only interrupts routed to the int signal:
Support for two processors.
— Interrupts can be routed to processor core 0 or 1
— Multi-cast delivery mode for interprocessor and global timer interrupts allowing these
Processor core initialization control
Programmable resetting of the PIC through the global configuration register
signalling error conditions that need to be addressed by software.
cores on the same device. (Can be used for self-interrupt in single-core devices.)
interprocessor communication.
on read. Used for cross-program communication.
– Eight 32-bit message interrupt channels.
– Two groups of four global 32-bit timers clocked with the CCB clock or the RTC input.
requests to int. Handling of such interrupt requests follows the OpenPIC specification, which
guarantees that the highest priority interrupt supersedes lower priority interrupts.
Section 9.4.1.2, “Interrupts Routed to
interrupts.
Section 9.4.1.1, “Interrupts Routed to cint or
this interrupt.
timer interrupts can only be routed to int.)
– Fully-nested interrupt delivery, guaranteeing that the interrupt source with the highest
– 16 programmable interrupt priority levels
– Support for identifying and handling spurious interrupts
interrupts to be routed to either core 0 or 1, or both cores.
Timers within each group can be concatenated to time longer durations.
priority is given precedence over lower priority interrupts, including any that are in service.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
int,” describes how the PIC logic handles these
IRQ_OUT,” describes how the PIC logic supports
Programmable Interrupt Controller (PIC)
9-3