MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 140

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Memory Map
2.2.3.2
The local access IP block revision register 1 is shown in
Table 2-5
2.2.3.3
The local access IP block revision register 2 is shown in
Table 2-6
2-6
Offset 0x0_0BF8
Reset
Offset 0x0_0BFC
Reset
Local Memory
Offset (Hex)
W
W
16–23
24–31
R
R
0x0_0D48
0x0_0D50
0x0_0D68
0x0_0D70
0–15
8–15
Bits
Bits
0–7
0
0
describes LAIPBRR1 fields.
describes LAIPBRR2 fields.
IP_INT
IP_MN
IP_MJ
Name
Name
Local Access IP Block Revision Register 1 (LAIPBRR1)
Local Access IP Block Revision Register 2 (LAIPBRR2)
IP_ID
—
LAWBAR10—Local access window 10 base address register
LAWAR10—Local access window 10 attribute register
LAWBAR11—Local access window 11 base address register
LAWAR11—Local access window 11 attribute register
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 2-2. Local Access IP Block Revision Register 1 (LAIPBRR1)
Figure 2-3. Local Access IP Block Revision Register 2 (LAIPBRR2)
IP block ID
Major revision
Minor revision
Reserved
IP block integration options
Table 2-4. Local Access Register Memory Map (continued)
IP_ID
7
8
Table 2-5. LAIPBRR1 Field Descriptions
Table 2-6. LAIPBRR2 Field Descriptions
Register
IP_INT
All zeros
All zeros
15 16
15 16
Figure
Description
Figure
Description
2-2.
2-3.
IP_MJ
Access
R/W
R/W
R/W
R/W
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
23 24
23 24
Reset
Freescale Semiconductor
Access: Read only
Access: Read only
IP_CFG
IP_MN
Section/Page
2.2.3.5/2-7
2.2.3.5/2-7
2.2.3.5/2-7
2.2.3.5/2-7
31
31