MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 835

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 14-56
14.5.3.6
This section describes the MIB registers. The eTSEC RMON module has 37 separate statistics counters,
which simply count or accumulate statistical events that occur as packets transmitted and received. These
counters support RMON MIB group 1, RMON MIB group 2 if table counters, RMON MIB group 3,
RMON MIB group 9, RMON MIB 2, and the IEEE 802.3 Ethernet MIB.
An interrupt can be generated upon any one counter’s rollover condition through a carry interrupt output
from the RMON. Each counter’s rollover condition can be discretely masked from causing an interrupt by
internal masking registers. In addition, each individual counter value may be reset on read access, or all
counters may be simultaneously reset by setting ECNTRL[CLRCNT].
The majority of MIB counters are Ethernet-specific.
In FIFO modes, only the following registers are updated:
Freescale Semiconductor
•
•
16–31
8–15 Exact Match Address, 1st Octet
0–7
Transmit: TBYT, TPKT, TDRP
Receive: RBYT, RPKT, RFCS
Bit
Exact Match Address, 2nd Octet
describes the fields of a MACxADDR2 register.
MIB Registers
RMON counters do not comprehend custom VLAN tagged frames.
Affected counters include TRMGV, RMCA, RBCA, RXCF, RXPF, RXUO,
RALN, RFLR, ROVR, RJBR, TMCA, TBCA, TXPF, TXCF. Specifically,
custom VLAN tagged frames are not afforded the ability to be greater than
1518, as compared to the IEEE standard tagged frames.
The transmit and receive frame counters (TR64, TR127, TR 255, TR511,
TR1K, TRMAX, adn TRMGV) do not increment for aborted frames
(collision retry limit exceeded, late collision, underrurn, EBERR, TxFIFO
data error, frame truncated due to exceeding MAXFRM, or excessive
deferral).
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 14-58. MAC01ADDR2–MAC15ADDR2 Field Descriptions
Name
—
This field holds the second octet of the exact match address. The
second octet (destination address bits 8–15) defaults to a value of
0x0.
This field holds the first octet of the exact match address. The first
octet (destination address bits 0–7) defaults to a value of 0x0.
Reserved
NOTE
NOTE
Description
Enhanced Three-Speed Ethernet Controllers
14-87