MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 553

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.7.5.6
The KEU interrupt status register tracks the state of possible errors, provided those errors are not masked,
through the KEU interrupt control register.
The KEU interrupt status register indicates the unmasked errors that have occurred and have generated the
ERROR interrupt signals to the channel. Each bit in this register can only be set if the corresponding bit of
the KEU interrupt mask register is zero (see
(KEUIMR)”).
If the KEU interrupt status register is non-zero, the KEU halts and the KEU ERROR interrupt signal is
asserted to the controller (see
KEU is being operated through channel-controlled access, then an interrupt signal is generated to the
channel to which the EU is assigned. The EU error then appears in the bit 55 of the channel pointer status
register (for more information, see
the controller.
This register can be cleared by setting the RI bit of the KEU reset control register. If a KEU error is reported
by the channel while operating in descriptor mode, the user can rely on the channel to clear the KEU
interrupt by writing the Continue bit in the channel configuration register (for more information, see
Section 10.4.4.1, “Channel Configuration Register
KEU to signal the corresponding error, unless the associated error has been masked in the KEU interrupt
mask register.
Freescale Semiconductor
59-60
Bits
61
62
63
KEU Interrupt Status Register (KEUISR)
Name
ICCR
RD
EI
DI
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 10-55. KEU Status Register Fields Description (continued)
Integrity check comparison result.
00 No integrity check comparison was performed.
01 The integrity check comparison passed.
10 The integrity check comparison failed.
11 Reserved
Note: A passed or failed result is generated only if ICV checking is enabled and the algorithm
Error interrupt. Reflects the state of the ERROR interrupt signal, as sampled by the controller
interrupt status register
0 KEU is not signaling error
1 KEU is signaling error
Done interrupt. Reflects the state of the DONE interrupt signal, as sampled by the controller
interrupt status register
0 Processing not done
1 All bytes processed
Reset done. Indicates when the KEU has completed its reset sequence, as reflected in the signal
sampled by the appropriate channel.
0 Reset in progress
1 Reset done
selected is f9.
Section 10.5.4.2.2, “Interrupt Status Register
Table 10-15 on page
(Section 10.5.4.2.2, “Interrupt Status Register
(Section 10.5.4.2.2, “Interrupt Status Register
Section 10.7.5.7, “KEU Interrupt Mask Register
(CCR)”). Setting any error bit in this register causes the
10-43) and generates a channel error interrupt to
Description
(ISR)”). In addition, if the
(ISR)”).
(ISR)”).
Security Engine (SEC) 3.0
10-123