MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1003

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.3.1.7
The destination address registers, shown in
controller writes data.
In direct mode, if MRn[SRW] is set and MRn[CDSM/SWSM] is cleared, a write to this register
simultaneously sets MRn[CS], starting a DMA transfer. Software must ensure that this is a valid address.
Table 15-12
Freescale Semiconductor
12–15
16–27
28–31
8–11
0–31
Offset 0x11C
Bits
Reset
Bits
7
W
R
0x19C
0x21C
0x29C
DWRITETTYPE DMA destination transaction type. Reserved values result in a programming error being detected
0
Name
DAD
DSME
Name
EDAD
describes the field of the DARn.
—
—
Destination Address Registers (DAR n )
Destination address. This register contains the destination address of the DMA transfer. The contents are
updated after every DMA write operation unless the final stride of a striding operation is less than the stride
size, in which case it remains equal to the address from which the last stride began.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Destination stride mode enable
0 Stride mode disabled
1 Stride mode enabled
Ignored in basic mode (MR n [XFE] is cleared). Striding on the destination address can be
accomplished by setting DSME and setting the desired stride size and distance in DSR n .
Reserved
and logged in SR[PE].Transaction type to run on local address space
0000–0011 Reserved
0100 Write, don’t snoop local processor
0101 Write, snoop local processor
0110
0111
1000–1111 Reserved
Reserved
Extended destination address. EDAD represents the four high-order bits of the 36-bit destination
address.
Figure 15-12. Destination Address Registers (DAR n )
Table 15-11. DATR n Field Descriptions (continued)
Table 15-12. DAR n Field Descriptions
Figure
15-12, contain the addresses to which the DMA
All zeros
DAD
Description
Description
Access: Read/Write
DMA Controller
15-17
31