MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 784

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14-36
20–24
Bits
18
19
25
26
27
28
29
AUTOZ
R100M
GMIIM
Name
STEN
TBIM
RMM
RPM
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Automatically zero MIB counter values and carry registers.
0 The user must write the addressed counter zero after a host read.
1 The addressed counter value is automatically cleared to zero after a host read.
This is a steady state signal and must be set prior to enabling the Ethernet controller and must not be
changed without proper care.
MIB counter statistics enabled.
0 Statistics not enabled
1 Enables internal counters to update
This is a steady state signal and must be set prior to enabling the Ethernet controller and must not be
changed without proper care.
Reserved
GMII interface mode. If this bit is set, a PHY with a GMII or RGMII interface is expected to be connected.
If cleared, a PHY with an MII or RMII interface is expected. The user should then set
MACCFG2[I/F Mode] accordingly. The state of this status bit is defined during power-on reset. See
Section 4.4.3, “Power-On Reset Configuration.”
0 MII or RMII mode interface expected
1 GMII or RGMII mode interface expected
Ten-bit interface mode. If this bit is set, ten-bit interface mode is enabled. This bit can be pin-configured
at reset to set or clear. See
0 GMII or MII or RMII mode interface
1 TBI mode interface
Ethernet and FIFO interfaces. RPM and RMM are never set together. This register can be
pin-configured at reset to 0 or 1. See
0 GMII or MII or TBI in non-reduced-pin mode configuration
1 RGMII or RTBI reduced-pin mode
RGMII/RMII 100 mode. This bit is ignored unless SGMIIM, RPM or RMM are set and MACCFG2[I/F
Mode] is assigned to 10/100 (01).
0 RGMII is in 10 Mbps mode
1 RGMII is in 100 Mbps mode
This bit must be cleared for 1-Gbps SGMII operation.
Reduced-pin mode for 10/100 interfaces. If this bit is set, an RMII pin interface is expected. RMM must
be 0 if RPM = 1. This register can be pin-configured at reset to 0 or 1. See
Reset Configuration.”
0 Non-RMII interface mode
1 RMII interface mode
Reduced-pin mode for Gigabit interfaces. If this bit is set, a reduced-pin interface is expected on either
SGMII is in 10 Mbps mode, and every 100th SGMII Reference clock is used to transfer data
SGMII is in 100 Mbps mode, and every 10th SGMII Reference clock is used to transfer data
FIFO configured for 8-bit operation
RMII is in 10 Mbps mode, and every 10th RMII Reference clock is used to transfer data
RMII is in 100 Mbps mode, and data is transferred on every Reference clock
Table 14-11. ECNTRL Field Descriptions (continued)
Section 4.4.3, “Power-On Reset Configuration.”
Section 4.4.3, “Power-On Reset Configuration.”
Description
Section 4.4.3, “Power-On
Freescale Semiconductor