MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 206

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reset, Clocking, and Initialization
on-chip ROM in boot ROM location (see
ROM. The on-chip ROM is selected by configuring the POR config pins cfg_rom_loc[0:3].
After the device has completed the reset sequence, if the ROM location selects the on-chip ROM eSPI
Boot configuration, the e500 core starts to execute code from the internal on-chip ROM. The e500 core
configures the eSPI controller, enabling it to communicate with the external EEPROM. The EEPROM
should contain a specific data structure with control words, device configuration information and
initialization code. The on-chip ROM boot code uses the information from the EEPROM content to
configure the device, and to copy the initialization code to a target memory device (for example, the DDR)
through the eSPI interface. After all the code has been copied, the e500 core starts to execute the code from
the target memory device.
There are several different ways a user may utilise the eSPI boot feature. The simplest is for the on-chip
ROM to copy an entire operating system boot image into system memory, and then jump to it to begin
execution. However, this may be many megabytes and in some situations may sub-optimal.
A more advanced option is for the on-chip ROM to only copy a small user-customised subroutine, which
configures the eSPI in an optimal way. The user-customised subroutine then copies the rest of the boot
code potentially much faster than the on-chip ROM software can achieve. For example, the
user-customised subroutine may utilise Atmel RapidS or Winbond dual output eSPI modes.
4.5.1.2.2
4.5.1.2.3
The EEPROM should contain the initialization code length in bytes, source address in the eSPI EEPROM,
destination address in the target memory device, execution starting address, and multiple configuration
words with pairs of target address and its respective data.
4-36
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Provides mechanism to load initialization code from external eSPI EEPROM
Simple data structure in eSPI EEPROM
BOOT signature will be checked to validate that the EEPROM contains valid code
Supports variable code length in EEPROM
Flexible target memory device
Supports target memory configuration controlled by the user
Supports standard eSPI interface EEPROMs with read instruction code 0x03 followed by a 2-byte
address (16-bit addressable EEPROMs) or 3-byte address (24-bit addressable EEPROMs).
Initial setting will generate a serial clock below 5 MHz; the control word will allow for user
modification of clock frequency.
Features
EEPROM Data Structure
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table
4-14) causes the e500 CPU to fetch data from the on-chip
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