MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 679

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.3.1.18 Flash Instruction Register (FIR)
The local bus Flash instruction register (FIR), shown in
instructions for issue by the FCM. Setting FMR[OP] non-zero and writing LSOR or accessing a bank
controlled by FCM causes FCM to read FIR 4 bits at a time, starting at bit 0 and continuing with adjacent
4-bit opcodes, until only NOP opcodes remain. The programmed instruction sequence of OP0, OP1,...,
OP7 is performed on the activated bank, using the data buffer addressed by FPAR. If LTEIR[CCI] = 1 and
LTEDR[CCD] = 0, eLBC will generate an interrupt once the entire sequence has completed, and software
should examine LTEATR and clear its V bit.
Freescale Semiconductor
Offset 0x0_50E4
Reset
Software must not alter the contents of the addressed FCM buffer, FIR, MDR, FCR, FBAR, FPAR, or
FBCR while an operation is in progress—or eLBC will behave unpredictably—but software can freely
modify the contents of any currently unused FCM RAM buffer in preparation for the next operation.
26–27
28–29
30–31
Bits
W
R
0
Name
OP0
OP
AL
—
3
Address length. AL sets the number of address bytes issued during page address (PA) operations.
However, the number of address bytes issued for column address (CA) operations is determined by
the device page size (for OR n [PGS] = 0, 1 CA byte is issued; for OR n [PGS] = 1, 2 CA bytes are issued).
00 2 bytes are issued for page addresses, thus a total of 3 (OR n [PGS] = 0) or 4 (OR n [PGS] = 1)
01 3 bytes are issued for page addresses, thus a total of 4 (OR n [PGS] = 0) or 5 (OR n [PGS] = 1)
10 4 bytes are issued for page addresses, thus a total of 5 (OR n [PGS] = 0) or 6 (OR n [PGS] = 1)
11 —
Reserved
Flash operation. For OP not equal to 00, a special operation is triggered on the next write to LSOR or
dummy access to a bank controlled by FCM. Once a special operation has commenced, OP is
automatically reset to 00 by FCM. Individual blocks may be temporarily unlocked for erase and
reprogramming operations.
00 Normal operation. All read and write accesses to banks controlled by FCM access the shared FCM
01 Simulate auto-boot block loading, and set FMR[BOOT]. Boot block loading occurs from the bank
10 Execute the command sequence contained in FIR, but with write protection enabled (pin LFWP
11 Execute the command sequence contained in FIR, but permit the single block identified by
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
4
address bytes are issued for a {CA,PA} sequence
address bytes are issued for a {CA,PA} sequence
address bytes are issued for a {CA,PA} sequence
buffer RAM. No bus activity is caused by this operation.
triggered on the special operation, therefore the appropriate bank configuration must be initialized
prior to issuing this operation.
asserted low) so that all Flash blocks are protected from accidental erasure and reprogramming.
FBAR[BLK] to be erased or reprogrammed, with pin LFWP remaining high during the access.
OP1
Table 13-24. FMR Field Descriptions (continued)
7
8
Figure 13-22. Flash Instruction Register
OP2
11 12
OP3
All zeros
15 16
Description
Figure
OP4
13-22, holds a sequence of up to eight
19 20
OP5
23 24
Enhanced Local Bus Controller
OP6
Access: Read/Write
27 28
OP7
13-37
31