MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 691

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 13-35
can configure ORn[ACS] to specify LCS to meet this requirement. Generally, the attributes for the
memory cycle are taken from ORn. These attributes include the CSNT, ACS, XACS, SCY, TRLX, EHTR
and SETA fields.
13.4.2.1
The basic GPCM read timing parameters that may be set by the ORn attributes are shown in
The read access cycle commences upon latching of the memory address (LALE negated), and concludes
when LBCTL returns high to turn the local bus around for a subsequent address phase. Read data is
captured by eLBC on the falling edge of TA. LOE and LCSn negate high simultaneously, in some cases
before the end of the read access to provide additional hold time for the external memory.
Freescale Semiconductor
shows LCS as defined by the setup time required between the address lines and CE. The user
GPCM Read Signal Timing
eLBC in GPCM
Figure 13-35. GPCM Basic Read Timing (XACS = 0, ACS = 1x, TRLX = 0)
Mode
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
A[19:5]
LCS n
LALE
LCLK
LOE
LAD
Figure 13-34. Enhanced Local Bus to GPCM Device Interface
TA
LAD[0:31]
LA[27:31]
LWE0
LCS n
LALE
Address
LOE
ACS = 10
[12:26]
ACS = 11
[0:7]
Latch
Latched Address
Read Data
CE
OE
WE
Data[7:0]
A[4:0]
A[19:5]
Memory/Peripheral
Enhanced Local Bus Controller
Figure
13-36.
13-49