MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 729
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MPC8536E-ANDROID
Manufacturer Part Number
MPC8536E-ANDROID
Description
HARDWARE/SOFTWARE ANDROID OS
Manufacturer
Freescale Semiconductor
Series
PowerQUICC ™r
Type
MPUr
Datasheets
1.MPC8536EBVTAVLA.pdf
(127 pages)
2.MPC8536EBVTAVLA.pdf
(2 pages)
3.MPC8536EBVTAVLA.pdf
(1706 pages)
Specifications of MPC8536E-ANDROID
Contents
Board
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 729 of 1706
- Download datasheet (15Mb)
MxMR[AM] = 000
MxMR[AM] = 001
MxMR[AM] = 010
MxMR[AM] = 011
MxMR[AM] = 100
MxMR[AM] = 101
MxMR[AM] = 110
MxMR[AM] = 111
Note that any change to the AMX field from one RAM word to the next RAM word executed results in an
address phase on the {LADn, LAn} bus with the assertion of LALE for the number of cycles set for LALE
in the ORn and LCRR registers. The LGPL[0:5] signals maintain the value specified in the RAM word
during the LALE phase.
13.4.4.4.8
When a read access is handled by the UPM, and the UTA bit is 1 (data is to be sampled by the eLBC), the
value of the DLT3 bit in the same RAM word, in conjunction with MxMR[GPL4], determines when the
data input is sampled by the eLBC as follows:
Freescale Semiconductor
AMX = 10
AMX = 00
AMX = 10
AMX = 00
AMX = 10
AMX = 00
AMX = 10
AMX = 00
AMX = 10
AMX = 00
AMX = 10
AMX = 00
AMX = 10
AMX = 10
(Row)
(Row)
(Row)
(Row)
(Row)
(Row)
•
(Col)
(Col)
(Col)
(Col)
(Col)
(Col)
If MxMR[GPL4] = 1 (G4T4/DLT3 functions as DLT3) and DLT3 = 1 in the RAM word, data is
latched on the falling edge of the bus clock instead of the rising edge. The eLBC samples the data
on the next falling edge of the bus clock, which is during the middle of the current bus cycle. This
msb
0
AMX must not change values in any RAM word which begins a loop.
Data Valid and Data Sample Control (UTA)
1
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
2
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
3
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
4
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
5
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
6
Table 13-42. UPM Address Multiplexing
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
7
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NOTE
Internal Transaction Address
Reserved
Reserved
19 20 21 22 23 24 25 26 27 28 29 30
20 21 22 23 24 25 26 27 28 29 30
21 22 23 24 25 26 27 28 29 30
22 23 24 25 26 27 28 29 30
23 24 25 26 27 28 29 30
Enhanced Local Bus Controller
24 25 26 27 28 29 30
13-87
lsb
31
31
31
31
31
31
31
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