MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1013

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.4.1.1.4
Basic chaining single-write start mode allows a chain to be started by writing the current link descriptor
address register (CLNDARn). (Note that ECLNDARn must be written first so that the full 36-bit
descriptor address is present when the chain starts.) Setting MRn[CDSM/SWSM] in the mode register
causes MRn[CS] to be automatically set when the current link descriptor address register is written. The
sequence of events to start and complete a chain using single-write start mode is as follows:
15.4.1.2
The extended DMA mode also operates in chaining and direct mode. It offers additional capability over
the basic mode by supporting striding and a more flexible descriptor structure. This additional
functionality also requires a new and more complex programming model. The extended DMA mode is
activated by setting MRn[XFE].
15.4.1.2.1
Extended direct mode has the same functionality as basic direct mode with the addition of stride
capabilities. The bit settings are the same as in direct mode with the exception of the MRn[XFE] being set.
Striding on the source address can be accomplished by setting SATRn[SSME] and setting the desired stride
size and distance in SSRn. Striding on the destination address can be accomplished by setting
DATRn[DSME] and setting the desired stride size and distance in DSRn.
Freescale Semiconductor
4. Clear the mode register channel transfer mode bit, MRn[CTM], as well as MRn[XFE], to indicate
5. Clear, then set the mode register channel start bit, MRn[CS], to start the DMA transfer.
6. SRn[CB] is set by the DMA controller to indicate the DMA transfer is in progress.
7. SRn[CB] is automatically cleared by the DMA controller after finishing the transfer of the last
1. Set the mode register current descriptor start mode bit, MRn[CDSM/SWSM], and the extended
2. Build link descriptor segments in memory.
3. Poll the channel state (see
4. Initialize CLNDARn and ECLNDARn to point to the first descriptor segment in memory. This
5. SRn[CB] is set by the DMA controller to indicate the DMA transfer is in progress.
6. SRn[CB] is automatically cleared by the DMA controller after finishing the transfer of the last
basic chaining mode. Other control parameters may also be initialized in the mode register.
descriptor segment, or if the transfer is aborted (MRn[CA] transitions from a 0 to 1), or if an error
occurs during any of the transfers.
features enable bit MRn[XFE]. Also, clear the channel transfer mode bit, MRn[CTM]. This
initialization indicates basic chaining and single-write start mode. Also other control parameters
may be initialized in the mode register.
write automatically causes the DMA controller to begin the link descriptor fetch and set MRn[CS].
descriptor segment, or if the transfer is aborted (MRn[CA] transitions from a 0 to 1), or if an error
occurs during any of the transfers.
Extended DMA Mode Transfer
Basic Chaining Single-Write Start Mode
Extended Direct Mode
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table
15-23), to confirm that the specific DMA channel is idle.
DMA Controller
15-27