MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 904

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
Table 14-146
14.6.1.8
SGMII communication using the eTSEC is accomplished through the SerDes interface. See
page 14-7
14.6.2
This section describes how to connect an eTSEC to third-party communication devices, including users’
ASICs and FPGAs, through the FIFO interface.
Each eTSEC provides an 8-bit full-duplex packet FIFO interface port that bypasses the Ethernet MAC, but
re-uses the GMII signals. As a result, the FIFO interface normally does not impose the overheads of
Ethernet framing. The FIFO interface operates synchronously, at a maximum frequency defined by a ratio
of 4.2:1 (platform:TxClk) in GMII mode and 3.2:1 (platform:TxClk) in encoded mode providing OC-48
full-duplex transfer rates. For example, a FIFO frequency of 127 MHz in GMII mode requires a platform
frequency of 533 MHz; a FIFO frequency of 200 MHz in encoded mode requires a platform frequency of
667 MHz; a FIFO frequency of 167 MHz in encoded mode requires a platform frequency of 533 MHz.
The eTSEC Tx and Rx FIFOs, TOE functions, and DMA continue to be used in packet FIFO mode.
The ECNTRL[FIFM] bit determines whether eTSEC is communicating with its Ethernet MAC or FIFO
interface.
The following restrictions apply in any of the FIFO modes:
14-156
Bare IP packets—with an optional 32-bit CRC check sequence—can be transferred to the eTSEC directly.
•
•
8-bit packet FIFO
— The GMII signals of each eTSEC can be used to create a FIFO port, therefore eTSEC can
— The data signals of GMII and 8-bit FIFO remain the same. The data valid (RX_DV, TX_EN)
Transferred packets must be no more than 9600 bytes in length.
for specific signal assignments.
support up to two simultaneous 8-bit FIFO interfaces Choosing between 8-bit FIFO and
Ethernet affects each eTSEC independently, therefore a mix of FIFO and Ethernet interfaces
can be configured.
and error (RX_ER, TX_ER) signals are used to signal framing information. If required, the
collision (COL) and carrier sense (CRS) signals can be used in an encoded mode to provide
link-level flow control.
Connecting to FIFO Interfaces
SGMII Interface
describes the signals shared by all interfaces.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
GTX_CLK125
Signals
MDIO
MDC
Sum
Table 14-146. Shared Signals
I/O
I/O
O
I
No. of Signals
1
1
1
3
Management interface clock
Management interface I/O
Reference clock
Function
—
Freescale Semiconductor
Table 14-1 on