MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 367

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Parameter
OBC_CFG
ODT_CFG
ZQ_EN
WWT
RWT
WRT
RRT
Table 8-69. Programming Differences Between Memory Types (continued)
ODT Configuration
On-The-Fly Burst Chop
Configuration
Read-to-write turnaround
for same chip select (in
TIMING_CFG_4)
Write-to-read turnaround for
same chip select (in
TIMING_CFG_4)
Read-to-read turnaround for
same chip select (in
TIMING_CFG_4)
Write-to-write turnaround
for same chip select (in
TIMING_CFG_4)
ZQ Calibration Enable
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Description
DDR3
DDR2
DDR3
DDR2
DDR3
DDR2
DDR3
DDR2
DDR3
DDR2
DDR3
DDR2
DDR3
DDR2
system topology. Typically, if ODT is enabled, then
the internal IOs should be set up for termination
only during reads to DRAM.
system topology. Typically, if ODT is enabled, then
the internal IOs should be set up for termination
only during reads to DRAM.
Should be set to 0
This is expected to give the best performance in
DDR3 mode. This feature can only be used if a
64-bit data bus is used.
Should typically be set to 0000
turnaround time when accessing the same chip
select. This is useful for burst chop mode, as there
are some timing requirements to the same chip
select that still must be met.
Should typically be set to 0000
time between a write and read to the same chip
select. This is useful for burst chop mode.
However, it is expected that
TIMING_CFG_1[WRTORD] is programmed
appropriately such that TIMING_CFG_4[WRT]
can be set to 0000.
Should typically be set to 0000
(on-the-fly or fixed).
Should typically be set to 0000
(on-the-fly or fixed).
Should be set to 0
DDR_ZQ_CNTL should also be programmed
appropriately based on the DRAM specifications.
Can be set for termination at the IOs according to
Can be set for termination at the IOs according to
Can be set to 1 if on-the-fly burst chop is used.
This can be used to force a longer read-to-write
This could be used to force a certain turnaround
Should typically be set to 0100 in burst chop mode
Should typically be set to 0100 in burst chop mode
Should be set to 1. The other fields in
Differences
DDR Memory Controller
Section/page
8.4.1.18/8-36
8.4.1.18/8-36
8.4.1.18/8-36
8.4.1.18/8-36
8.4.1.20/8-39
8.4.1.9/8-26
8.4.1.9/8-26
8-93