MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1251

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.3.4.2
TransStatus, shown in
Table 19-18
19.3.4.3
LinkCfg, shown in
Table 19-19
Freescale Semiconductor
Offset 0x1_8148
Reset
Reset 1
Offset
31–27
Reset
Bit
26
W
W
R
R
W
R
31
15
0x1_8144
15
1
describes the TransStatus fields.
describes the LinkCfg fields.
Transport Layer Status Register (TransStatus)
Link Layer Configuration Register (LinkCfg)
Name
—
POE
1
—
Figure
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
1
AR
Figure
Figure 19-18. Transport Layer Status Register (TransStatus)
27
15–8
1
Figure 19-19. Link Layer Configuration Register (LinkCfg)
7–0
Bit
19-19, controls the configuration of the link layer.
Reserved
Primitive override enable. When set, this bit enables the replacement of a single primitive, as
specified by CFG_PRIM/CFG_CD, when the link layer state machine is in the
CFG_PRIM_OVR_STATE state. This bit has to be toggled from a 0 to a 1 to enable this
feature.
POE
26
1
TX_SM
19-18, can be read to determine the status of the transport layer.
Table 19-18. TransStatus Field Descriptions
25
1
Table 19-19. LinkCfg Field Descriptions
RX_SM
TX_SM
Name
1
8
EPNRT S4A
0
7
Indicates the state of Tx state machine.
Indicates the state of Rx state machine.
6
0
All zeros
8
RX_SCR
_EN
1
5
Description
7
Description
TX_SCR
_EN
1
4
PRT
TX_PRIM
_JUNK
0
3
RX_SM
TX_CO
NT_EN
1
2
Access: Read/Write
RX_BAD
Access: Read only
_CRC
0
1
SATA Controller
TX_BAD
_CRC
16
0
19-21
0
0