MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 50

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
23.5.1.14.5
23.5.1.15
23.5.1.16
23.5.1.16.1
23.5.1.16.2
23.5.1.16.3
23.5.1.16.4
24.1
24.1.1
24.1.2
24.2
24.3
24.3.1
24.3.2
24.3.2.1
24.3.2.2
24.3.3
24.3.3.1
24.4
24.4.1
24.4.2
24.4.3
24.4.4
24.4.5
24.4.6
24.4.7
24.4.8
25.1
25.1.1
25.1.2
25.1.3
25.1.3.1
25.1.3.2
l
Introduction.................................................................................................................... 24-1
Signal Descriptions ........................................................................................................ 24-3
Memory Map and Register Definition........................................................................... 24-3
Functional Description................................................................................................. 24-11
Introduction.................................................................................................................... 25-1
Overview.................................................................................................................... 24-2
Features...................................................................................................................... 24-3
Register Summary...................................................................................................... 24-3
Control Registers ....................................................................................................... 24-5
Counter Registers..................................................................................................... 24-10
Performance Monitor Interrupt................................................................................ 24-11
Event Counting ........................................................................................................ 24-12
Threshold Events ..................................................................................................... 24-12
Chaining................................................................................................................... 24-13
Triggering ................................................................................................................ 24-13
Burstiness Counting................................................................................................. 24-14
Performance Monitor Events ................................................................................... 24-16
Performance Monitor Examples .............................................................................. 24-27
Overview.................................................................................................................... 25-1
Features...................................................................................................................... 25-3
Modes of Operation ................................................................................................... 25-3
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
External Power Supply Control ........................................................................... 23-59
Low Power Considerations.................................................................................. 23-60
Performance Monitor Global Control Register (PMGC0) .................................... 24-5
Performance Monitor Local Control Registers (PMLCAn, PMLCBn)................. 24-6
Performance Monitor Counters (PMC0–PMC9)................................................. 24-10
Local Bus (LBC) Debug Mode.............................................................................. 25-4
DDR SDRAM Interface Debug Modes ................................................................. 25-4
eTSEC Wake-on-LAN—ARP (User Defined) Packet .................................... 23-59
POWER_OK Input Signal............................................................................... 23-60
POWER_EN Output Signal............................................................................. 23-61
DPSLP Register Bit ......................................................................................... 23-61
RST_DPSLP Register Bit................................................................................ 23-61
Debug Features and Watchpoint Facility
Device Performance Monitor
Contents
Chapter 24
Chapter 25
Title
Freescale Semiconductor
Number
Page