MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1351

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.3.2.4
In host mode, this register is used by the controller to index the periodic frame list. The register updates
every 125 microseconds (once each microframe). Bits N–3 are used to select a particular entry in the
periodic frame list during periodic schedule execution. The number of bits used for the index depends on
the size of the frame list as set by system software in USBCMD[FS].
This register must be written as a DWord. Byte writes produce-undefined results. This register cannot be
written unless the USB controller is in the Halted state as indicated by the USBSTS[HCH]. A write to this
register while USBCMD[RS] is set produces undefined results. Writes to this register also affect the SOF
value.
In device mode, this register is read-only and, the USB controller updates the FRINDEX[13–3] register
from the frame number indicated by the SOF marker. Whenever a SOF is received by the USB bus,
FRINDEX[13–3] is checked against the SOF marker. If FRINDEX[13–3] is different from the SOF
marker, FRINDEX[13–3] is set to the SOF value and FRINDEX[2–0] is cleared (that is, SOF for 1 msec
frame). If FRINDEX[13–3] is equal to the SOF value, FRINDEX[2–0] is incremented (that is, SOF for
125-µsec microframe.)
Freescale Semiconductor
Offset 0x14C
Reset 0 0
Bits
2
1
0
W
R
31
Name
PCE
UEE
UE
Frame Index Register (FRINDEX)
0
Port change detect enable. When this bit is a one, and USBSTS[PCI] is a one, the controller will issue an
interrupt. The interrupt is acknowledged by software clearing USBSTS[PCI].
0 Disable
1 Enable
USB error interrupt enable. When this bit is a one, and USBSTS[UEI] is a one, the controller will issue an
interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing USBSTS[UEI].
0 Disable
1 Enable
USB interrupt enable. When this bit is a one, and USBSTS[UI] is a one, the controller will issue an interrupt
at the next interrupt threshold. The interrupt is acknowledged by software clearing USBSTS[UI].
0 Disable
1 Enable
0 0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 21-11. USBINTR Register Field Descriptions (continued)
0
0 0 0 0 0 0 0 0 0 0 0
Figure 21-11. USB Frame Index (FRINDEX)
—
Description
14 13
0
n n n n n n n n n n n n n n
FRINDEX
Universal Serial Bus Interfaces
Access: Read/Write
21-17
0