MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1548

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Global Utilities
setting the appropriate HID0 bit, typically at system start-up time. Setting WE has no direct effect on
instruction execution, but is reflected on the internal doze, nap, and sleep signals, depending on the HID0
settings. To ensure a clean transition into and out of a power-saving mode, the following program sequence
is recommended:
23.5.1.12 Requirements for Reaching and Recovering from Sleep State
In order to successfully reach the sleep state, I/O traffic to the device must be stopped. The logic that
controls the power down sequence waits for all I/O interfaces to become idle. In some applications this
may happen eventually without actively shutting down interfaces, but most likely, software will have to
take steps to shut down the eTSEC, PCI, PCI Express and USB device interfaces before issuing the
command (either the write to the core MSR[WE] as described above or writing to POWMGTCSR) to put
the device into sleep state.
The exception to this is that interfaces used for wake (USB or eTSEC) do not need to be shut down if they
are the desired source of wake-up.
Prior to entering a sleep state, the SATA interface should be stopped with the following sequence:
Upon exiting sleep mode, software should return these configuration bits to their normal state.
The PCI interfaces will begin retrying inbound transactions before entering a power down state. The PCI
interfaces, however, could potentially be in an unknown state when they exit sleep if they were in the
middle of a retry sequence when internal clocks were shut down. Therefore it is strongly recommended
that system software clear the memory space bit in the PCI Bus Command Register before putting the
device in sleep mode. Software may also need to set the Agent Config Lock bit of the PCI Bus Function
Register so that the device will not respond to configuration transactions. Upon exiting sleep mode,
software should return these configuration bits to their normal state.
As described in
flushed if coherency is required.
23.5.1.13 Requirements for Reaching and Recovering from Deep Sleep State
In order for the device to transition to the deep sleep state, POWMGTCSR[DPSLP] must be set. As part
of this process, the system automatically transitions through the sleep state before entering deep sleep.
Software will have to take steps to map the boot vector to the warm reset boot code and to program all
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1. Confirm that all commands are completed by checking Command Queue Register (CQR).
2. Write SControl[SPM] to 4'b0010 to initiate slumber mode power management. This will notify
3. Poll SStatus[IPM] for 4'b0110 to confirm interface is in slumber mode power management.
4. Optional: Write HControl[HC_On] to 1'b0 to ask sataHost to go offline. This places the PHY in
5. Optional: Poll HStatus[HS_On] for 1'b0 to confirm that sataHost is offline.
the device to go into slumber mode.
reset and saves additional power.
Section 23.5.1.10, “Snooping in Power-Down Modes (e500)”,
loop:
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
sync
mtmsr (WE)
isync
br loop
the L1 caches should be
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